Hello all, I'm trying to modify the TLB code for SimpleTimingCPU, but one thing I can't seem to find is what the latency of a DTLB miss is. I found the code in NDtbMissFault->invoke() for reading the page table mapping, but I can't seem to figure out if there's any mechanism for stalling the CPU to handle the fault.
Reading the wiki for the SImpleTimingCPU, it sounds like it isn't meant to model this kind of detail. So is it just a one cycle fetch penalty for handling a TLB miss? If this is the case, what's the simplest CPU model that will actually stall for TLB misses? Thanks, Paul
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