Hi All,
I have a questions to ask about x86 CPU:
why are all "lock prefix instruction" translated to Microops with "mfence"
pair?
Ex. "lock inc [eax]" trans to:
"""
mfence
ldstl t1, seg, sib, disp
addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
stul t1, seg, sib, disp
mfence
"""
I checked the "ldstl" and "stul" microops, both of them have the flag
"Request::LOCKED". I think this flag should guarantee the "lock" semantics.
Does somebody can give me some reasons?
Regards,
Hawk
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
