Hi Pritha,
It looks like you're correct for (1) at first glance.
With regards to (2) it seems as though v2.5 of the manual said cache
line == 1, descriptor == 0; while the latest version reversed that. It's
listed as a change in the manual, so it was probably a misprint.
Finally, with regards to (3) look at the tadvProcess(), and
tadvProcess() functions which writeback all descriptors before signaling
the interrupt.
It would be great if you could create, test and post a
patch to address (1), and (2).
Thanks,
Ali
On 25.02.2012 13:22,
Pritha Ghoshal wrote:
> Hi,
> I have a confusion in the writeback
section for the transmission descriptors.
> According to the IGBE_e1000
documentation, the TX Descriptor should be written back in 3 cases :
>
1. If Wthresh = 0,
> 2. If Used size > Wthresh . This has 2 levels of
granularity:
> a) Cache line (Gran = 0)
> b) Descriptor (Gran = 1)
>
3. When interrupt timer expires.
> if (igbe->regs.txdctl.wthresh() ==
0) {
> igbe->anBegin("TXS", "Desc Writeback");
> DPRINTF(EthernetDesc,
"WTHRESH == 0, writing back descriptorn");
> writeback(0);
> } else if
(igbe->regs.txdctl.gran() && igbe->regs.txdctl.wthresh() >=
>
descInBlock(usedCache.size())) {
> DPRINTF(EthernetDesc, "used >
WTHRESH, writing back descriptor 1 thresh:%d, size=%d cache_sizen",
igbe->regs.txdctl.wthresh(), usedCache.size(),igbe->cacheBlockSize());
> igbe->anBegin("TXS", "Desc Writeback");
>
writeback((igbe->cacheBlockSize()-1)>>4);
> } else if
(igbe->regs.txdctl.wthresh() >= usedCache.size()) {
>
DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor 2
thresh:%d, size=%dn", igbe->regs.txdctl.wthresh(), (usedCache.size()));
> igbe->anBegin("TXS", "Desc Writeback");
>
writeback((igbe->cacheBlockSize()-1)>>4);
> }
> The following are my
questions:
> 1. In the piece of code, it seems that the check condition
is always that Wthresh > size, not the other way around - size>Wthresh.
> 2. When gran = 1, the granularity should be descriptor, but when gran
= 1, it goes into the first else condition, which checks how many cache
blocks are used by the descriptor. Shouldn't this condition be in the
second else condition?
> 3. The timer interrupt does not seem to be
there..
> Am I misunderstanding something?
> Thanks,
> Pritha
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