How does x86 implement locked transactions? Are they done via load locked/store conditionals?
Ali Sent from my ARM powered mobile device On Mar 2, 2012, at 10:53 PM, Gabe Black <[email protected]> wrote: > I dug into this some more, and it looks like it really is because the memory > system doesn't enforce locking a particular address. Specifically here: > > 5049193421500: system.cpu0 T0 : @_spin_lock_irqsave+3.1 : DEC_LOCKED_M : > ldstl t1d, DS:[rdi] : MemRead : D=0x0000000000000000 A=0xffffffff80768400 > 5049193435000: system.cpu1 T0 : @generic_unplug_device+24.0 : MOV_R_M : ld > rax, DS:[rbx + 0x180] : MemRead : D=0xffffffff80768400 A=0xffff8100075f62c8 > 5049193436000: system.cpu1 T0 : @generic_unplug_device+31.0 : MOV_M_I : > limm t1d, 0x1 : IntAlu : D=0x0000000000000001 > 5049193421500: system.cpu0 T0 : @_spin_lock_irqsave+3.2 : DEC_LOCKED_M : > subi t1d, t1d, 0x1 : IntAlu : D=0x0000000000000094 > 5049193421500: system.cpu0 T0 : @_spin_lock_irqsave+3.3 : DEC_LOCKED_M : > stul t1d, DS:[rdi] : MemWrite : D=0x00000000ffffffff A=0xffffffff80768400 > 5049193436000: system.cpu1 T0 : @generic_unplug_device+31.1 : MOV_M_I : st > t1d, DS:[rax] : MemWrite : D=0x0000000000000001 A=0xffffffff80768400 > > > You can more or less see where accesses to a spin lock are getting jumbled > and the spin lock getting set to -1 because one CPU is clobbering the other's > store. Shortly after that point, CPU 1 seems to go to sleep, and CPU 0 spins > forever waiting for that -1 to become a 0. > > > \/\/\/\/ > So if any of you memory system folks are reading this, the memory system not > respecting the lock request flags is a fairly serious problem that really > deserves some attention. > /\/\/\/\ > > Gabe > > > > On 02/26/12 04:51, Gabe Black wrote: >> >> I looked into this more, and the code that sets up the memory hierarchy >> was broken a little while ago. I have a patch that seems to fix it >> (attached) but then it gets stuck a little later. I remember a while ago >> someone had problems with atomic operations not being supported by the >> memory system fully, but I don't remember the specifics. This might be >> that problem too. >> >> Gabe >> >> On 02/24/12 02:45, Gabriel Michael Black wrote: >>> Yes, I have. You're using O3 though, and that support is fairly new. >>> >>> Gabe >>> >>> Quoting "Ankita (Garg) Goel" <[email protected]>: >>> >>>> Hi, >>>> >>>> Has anyone been able to boot multiple cpus wth FS mode on x86 ? If >>>> yes, it >>>> would greatly help if you could share your environmental setup. The >>>> issues >>>> I am facing I have already posted in some previous emails. >>>> >>>> Thanks for your help! >>>> >>>> -- >>>> Regards, >>>> Ankita >>>> >>> >>> >>> _______________________________________________ >>> gem5-users mailing list >>> [email protected] >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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