Pritha, There should be a "UpdatePredictor" command that needs to be in there. In the clean tree, should be around line 548 in cpu.cc
On Sat, Mar 3, 2012 at 11:28 AM, Pritha Ghoshal <[email protected]> wrote: > Oh, I might have to modify the pred_history portion as well? In my case > sn3 was a branch and this squash is happening for sn7.. sn3 had apparently > finished committing.. Should it have cleared the pred_hist.front() at that > time? > > My BackEndStartStage value is 3. > > FrontEndSked function: > StageScheduler S0(res_sked, stage_num++); > StageScheduler S1(res_sked, stage_num++); > StageScheduler S2(res_sked, stage_num++); > > // Stage0 > S0.needs(FetchSeq, FetchSeqUnit::AssignNextPC); > S0.needs(ICache, FetchUnit::InitiateFetch); > > // Stage1 > S1.needs(ICache, FetchUnit::CompleteFetch); > S1.needs(Decode, DecodeUnit::DecodeInst); > S1.needs(BPred, BranchPredictor::PredictBranch); > S1.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC); > > //Stage2 > > > > Back end sked function > > int stage_num = ThePipeline::BackEndStartStage; > StageScheduler S3(res_sked, stage_num++); > StageScheduler S4(res_sked, stage_num++); > StageScheduler S5(res_sked, stage_num++); > StageScheduler S6(res_sked, stage_num++); > StageScheduler S7(res_sked, stage_num++); > StageScheduler S8(res_sked, stage_num++); > > if (!inst->staticInst) { > warn_once("Static Instruction Object Not Set. Can't Create" > " Back End Schedule"); > return NULL; > } > > // Stage 3 > S3.needs(RegManager, UseDefUnit::MarkDestRegs); > for (int idx=0; idx < inst->numSrcRegs(); idx++) { > if (!idx || !inst->isStore()) { > S3.needs(RegManager, UseDefUnit::ReadSrcReg, idx); > } > } > > //Stage 4 > if(inst->isMemRef()) { > S4.needs(AGEN,AGENUnit::GenerateAddr); > } > > > //Stage 5 > // Execution Unit > if (!inst->isNonSpeculative() && !inst->isMemRef()) { > if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) { > S5.needs(MDU, MultDivUnit::MultDiv); > } else { > S5.needs(ExecUnit, ExecutionUnit::ExecuteInst); > } > } > // DCache Initiate Access > if (inst->isMemRef()) { > // S5.needs(DTLB, TLBUnit::DataLookup); > if (inst->isLoad()) { > S5.needs(DCache, CacheUnit::InitiateReadData); > } else if (inst->isStore()) { > S5.needs(DCache, CacheUnit::InitiateWriteData); > } > } > > > > // Stage 6 > // --------------------------------------- > // DCache Complete Access > if (inst->isMemRef()) { > if (inst->isLoad()) { > S6.needs(DCache, CacheUnit::CompleteReadData); > } else if (inst->isStore()) { > S6.needs(DCache, CacheUnit::CompleteWriteData); > } > } > > // Stage 7 > // ------------------------------------------ > > // Stage 8 > // ----------------------------------------- > // NonSpeculative Execution > if (inst->isNonSpeculative() ) { > if (inst->isMemRef()) > fatal("Schedule doesnt handle Non-Speculative Memory > Instructions.\n"); > > S8.needs(ExecUnit, ExecutionUnit::ExecuteInst); > } > // Write Back to Register File > for (int idx=0; idx < inst->numDestRegs(); idx++) { > S8.needs(RegManager, UseDefUnit::WriteDestReg, idx); > } > > // Graduate Instructions > S8.needs(Grad, GraduationUnit::CheckFault); > S8.needs(Grad, GraduationUnit::GraduateInst); > > Pritha > > > > On Fri, Mar 2, 2012 at 7:13 PM, Korey Sewell <[email protected]> wrote: > >> >> I tried your code, with pred_hist.front().SeqNum <= squashed_sn, because >>> the last predicted instruction in my case was before the squashed >>> instruction.. >> >> I dont get this point. At the point of the TLB fault in graduation stage, >> the instruction causing the fault should be the oldest instruction in the >> pipe. >> >> In the scenario of a superscalar machine, their could be multiple >> instructions that commit in the same cycle. Even in this case, the branch >> should have already resolved in the execute stage and cleared it's >> prediction history. So their is no prediction history to squash there if >> it's reached the graduation stage. >> >> What is the sequence number for the instruction that you see in the >> prediction history? (is it 7?) >> >> >> Can you post what you have for "createFrontEndSked()" and >> "createBackEndSked()"? >> >> What is your "BackEndStartStage" value? >> >> I am not surprised you get a "unmapped access 0" error because if you go >> off on the wrong instruction path then it's possible to have a instruction >> or PC try to access address 0. >> >> Lastly, a trick I often use is run the same code with a simple cpu for >> the same amount of instructions that it takes to break the InOrder (or O3) >> and then compare the instruction traces so i know what values are supposed >> to be passed to younger instructions and have a better idea of what I'm >> looking for during debug. >> >> >> -- >> - Korey >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- - Korey
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