Hi, I have a question regarding using different cacheline sizes in Ruby Memory Simulations.
Using the --cacheline_size option it is possible to change the number of bytes each cache line is: but According to: http://gem5.org/Coherence-Protocol-Independent_Memory_Components simulating with anything other than the default 64 bytes would be "incorrect" since ruby uses the full physical address (the true addressable range) However, I tried using different cacheline ruby simulations, and noticed that in ruby.stats the rubySystem config still prints out the block size bytes to be 64 bytes. Looking at the config script, I noticed that the following line was missing in /configs/ruby/Ruby.py diff -r 09758345a3ac configs/ruby/Ruby.py --- a/configs/ruby/Ruby.py Tue Mar 06 22:43:49 2012 -0500 +++ b/configs/ruby/Ruby.py Wed Mar 07 01:53:31 2012 -0500 @@ -156,3 +156,4 @@ def create_system(options, system, piobu ruby.mem_size = total_mem_size ruby._cpu_ruby_ports = cpu_sequencers ruby.random_seed = options.random_seed + ruby.block_size_bytes = options.cacheline_size Correcting the script, the ruby.stats config output is correct, and ran a couple of simulations to verify program correctness. But I am not sure if there is something "wrong" with simulating using a cacheline size other than 64. Does using a line size other than 64 bytes implicitly reduce the possible addressable ranges? Or is the description on the wiki page incorrect? Could someone comment? Malek _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
