Hi Nathanaël, 

It appears as though that is the case. Have you
tried switching them and observed changes/issues? 

Thanks, 

Ali 

On
14.03.2012 06:48, Nathanaël Prémillieu wrote: 

> Hi everyone,
> I'm
currently looking at the *.isa file to see how the decoder is
generated.
> In the file arch/arm/isa/templates/pred.isa, in the
function
> "def template DataRegConstructor" (line 94), there is this
code:
> 
> 0 if (%(is_branch)s){
> 1 flags[IsControl] = true;
> 2
flags[IsIndirectControl] = true;
> 3 if (condCode == COND_AL || condCode
== COND_UC)
> 4 flags[IsCondControl] = true;
> 5 else
> 6
flags[IsUncondControl] = true;
> 7 }
> 
> Shouldn't line 4 and 6 be
inverted? Or I didn't really understand the 
> meaning of this two
flags.
> 
> Nathanaël Prémillieu
>
_______________________________________________
> gem5-users mailing
list
> gem5-users@gem5.org
>
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

 
_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Reply via email to