Hi Hongli,
I did manage to figure this out. Basically you need to check the ISA's
register using InUserMode() in the CPU Model, set a flag in the
packet, and then in the Sequencer/RubyPort code select the kind of
access permission for the rubyrequest based on if its in user mode or
not.
Here is a quick diff.
diff -r c1b35798353a -r ddce97e053ca src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Mon Oct 10 23:43:54 2011 -0400
+++ b/src/cpu/simple/timing.cc Mon Oct 10 23:44:36 2011 -0400
@@ -314,7 +314,7 @@
buildPacket(pkt, req, read, update, push);
// Check to see if inst is in user space
+ if(TheISA::inUserMode(tc)) {
pkt->setUserMode();
}
diff -r 8d1ff23c886f -r 32817ce13133 src/mem/packet.hh
--- a/src/mem/packet.hh Fri Sep 16 20:44:20 2011 -0400
+++ b/src/mem/packet.hh Sat Sep 17 22:00:03 2011 -0400
@@ -483,6 +483,7 @@
bool suppressFuncError() { return flags.isSet(SUPPRESS_FUNC_ERROR); }
void setUserMode() { flags.set(IS_USERMODE); }
+ bool isUserMode() { return flags.isSet(IS_USERMODE); }
// Flag to Indicate whether or not Packet corresponds to userspace app
+ static const FlagsType IS_USERMODE = 0x00010000;
Hope this helps.
Malek
On Mon, Mar 26, 2012 at 1:59 PM, Hongil Yoon <[email protected]> wrote:
> Hi all,
>
> I wanna analyze the memory operations from benchmarks: differentiating user
> part from kernel mode part. I inserted codes to filter the kernel part out
> in MESI_CMP_directory-L1$.sm(L1Cache_Wakeup.cc) based on the access mode
> variable whenever cache misses occur. All packets seem to be set as the
> supervisor access mode though the operations come from benchmarks.
>
> Some similar questions were posted here but I couldn't get the solution
> about it.
> http://www.mail-archive.com/[email protected]/msg00694.html
> http://www.mail-archive.com/[email protected]/msg00807.html
>
> Could you help me to figure this out?
>
> --
> Hongil
> _______________________________________________
> gem5-users mailing list
> [email protected]
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
