Hello,
I am working with some code that relies on the correct implementation of
the ARM CCSIDR (
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/CIHGGJAB.html)
control
register see: src/arch/arm/isa.cc:readMiscReg(). I'm trying to implement
this (and the CSSELR
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/CIHGGJAB.html)
and was wondering what is the best way to obtain cache information from
this location. E.g., currently I'm doing something like for the icache:
BaseCPU *_cpu = tc->getCpuPtr();
Cache<LRU> *iCache = dynamic_cast<Cache<LRU>*>(
_cpu->getPort("icache_port", 0)->getPeer()->getOwner());
CCSIDR ccsidr = 0;
ccsidr.linSize = (log2(_cpu->getPort("icache_port", 0)->peerBlockSize() >>
2)) - 2;
ccsidr.assoc = _cpu->getPort("icache_port",
0)->getPeer()->getOwner()->getTags()->getAsso() - 1;
etc...
The get functions, getTags(), getAssoc() are my own. But, is there a more
general way to do this? I.e., without having to go through the cpu,
explicitly using LRU, etc.?
--
Thanks,
Tony
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