I update my repository to the latest version (today) "changeset 8920"
Now I got a different error which is related to L2.
se.py is:
...
else:
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
CacheConfig.config_cache(options, system)
system.l2.prefetcher = StridePrefetcher(degree = 3, latency =
'10ns', size = 30)
root = Root(full_system = False, system = system)
Simulation.run(options, root, system, FutureClass)
As you can see I added the line which ali told. However I get this error:
File "/home/mahmood/gem5/src/python/m5/SimObject.py", line 716, in __getattr__
% (self.__class__.__name__, attr)
AttributeError: object 'System' has no attribute 'l2'
If it is possible for anyone (users/developers) please test and see if
that the prefetcher work properly or not.
Once the prefetcher is enabled crrectly, it must be NULL in config.ini
On 3/29/12, Mahmood Naderan <[email protected]> wrote:
> Ali,
> This is the complete error I get:
> mahmood@saturn:gem5-new$ build/X86/m5.debug configs/example/se.py -c
> tests/test-progs/hello/bin/x86/linux/hello
> gem5 Simulator System. http://gem5.org
> gem5 is copyrighted software; use the --copyright option for details.
>
> gem5 compiled Mar 23 2012 11:22:24
> gem5 started Mar 29 2012 13:27:22
> gem5 executing on saturn
> command line: build/X86/m5.debug configs/example/se.py -c
> tests/test-progs/hello/bin/x86/linux/hello
> Traceback (most recent call last):
> File "<string>", line 1, in <module>
> File "/home/mahmood/gem5-new/src/python/m5/main.py", line 357, in main
> exec filecode in scope
> File "configs/example/se.py", line 207, in <module>
> system.l2.prefetcher = StridePrefecher(degree = 3, latency =
> '10ns', size = 30)
> NameError: name 'StridePrefecher' is not defined
>
>
> the se.py is:
>
> import os
> import optparse
> import sys
> from os.path import join as joinpath
>
> import m5
> from m5.defines import buildEnv
> from m5.objects import *
> from m5.util import addToPath, fatal
>
> addToPath('../common')
> addToPath('../ruby')
>
> import Ruby
>
> import Simulation
> import CacheConfig
> from Caches import *
> from cpu2000 import *
>
> # Get paths we might need. It's expected this file is in
> m5/configs/example.
> config_path = os.path.dirname(os.path.abspath(__file__))
> config_root = os.path.dirname(config_path)
> m5_root = os.path.dirname(config_root)
>
> parser = optparse.OptionParser()
>
> # Benchmark options
> parser.add_option("-c", "--cmd",
> default=joinpath(m5_root, "tests/test-progs/hello/bin/%s/linux/hello" %
> \
> buildEnv['TARGET_ISA']),
> help="The binary to run in syscall emulation mode.")
> parser.add_option("-o", "--options", default="",
> help='The options to pass to the binary, use " " around the entire
> string')
> parser.add_option("-i", "--input", default="", help="Read stdin from a
> file.")
> parser.add_option("--output", default="", help="Redirect stdout to a
> file.")
> parser.add_option("--errout", default="", help="Redirect stderr to a
> file.")
>
> execfile(os.path.join(config_root, "common", "Options.py"))
>
> if '--ruby' in sys.argv:
> Ruby.define_options(parser)
>
> (options, args) = parser.parse_args()
>
> if args:
> print "Error: script doesn't take any positional arguments"
> sys.exit(1)
>
> multiprocesses = []
> apps = []
>
> if options.bench:
> apps = options.bench.split("-")
> if len(apps) != options.num_cpus:
> print "number of benchmarks not equal to set num_cpus!"
> sys.exit(1)
>
> for app in apps:
> try:
> if buildEnv['TARGET_ISA'] == 'alpha':
> exec("workload = %s('alpha', 'tru64', 'ref')" % app)
> else:
> exec("workload = %s(buildEnv['TARGET_ISA'], 'linux',
> 'ref')" % app)
> multiprocesses.append(workload.makeLiveProcess())
> except:
> print >>sys.stderr, "Unable to find workload for %s: %s" %
> (buildEnv['TARGET_ISA'], app)
> sys.exit(1)
> else:
> process = LiveProcess()
> process.executable = options.cmd
> process.cmd = [options.cmd] + options.options.split()
> multiprocesses.append(process)
>
>
> if options.input != "":
> process.input = options.input
> if options.output != "":
> process.output = options.output
> if options.errout != "":
> process.errout = options.errout
>
>
> # By default, set workload to path of user-specified binary
> workloads = options.cmd
> numThreads = 1
>
> if options.cpu_type == "detailed" or options.cpu_type == "inorder":
> #check for SMT workload
> workloads = options.cmd.split(';')
> if len(workloads) > 1:
> process = []
> smt_idx = 0
> inputs = []
> outputs = []
> errouts = []
>
> if options.input != "":
> inputs = options.input.split(';')
> if options.output != "":
> outputs = options.output.split(';')
> if options.errout != "":
> errouts = options.errout.split(';')
>
> for wrkld in workloads:
> smt_process = LiveProcess()
> smt_process.executable = wrkld
> smt_process.cmd = wrkld + " " + options.options
> if inputs and inputs[smt_idx]:
> smt_process.input = inputs[smt_idx]
> if outputs and outputs[smt_idx]:
> smt_process.output = outputs[smt_idx]
> if errouts and errouts[smt_idx]:
> smt_process.errout = errouts[smt_idx]
> process += [smt_process, ]
> smt_idx += 1
> numThreads = len(workloads)
>
> (CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
> CPUClass.clock = '2GHz'
> CPUClass.numThreads = numThreads;
>
> np = options.num_cpus
>
> system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
> physmem = PhysicalMemory(range=AddrRange("512MB")),
> membus = Bus(), mem_mode = test_mem_mode)
>
> for i in xrange(np):
> system.cpu[i].workload = multiprocesses[i]
>
> if options.fastmem:
> system.cpu[0].physmem_port = system.physmem.port
>
> if options.checker:
> system.cpu[i].addCheckerCpu()
>
> if options.ruby:
> if not (options.cpu_type == "detailed" or options.cpu_type ==
> "timing"):
> print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
> sys.exit(1)
>
> options.use_map = True
> Ruby.create_system(options, system)
> assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
>
> for i in xrange(np):
> ruby_port = system.ruby._cpu_ruby_ports[i]
>
> # Create the interrupt controller and connect its ports to Ruby
> system.cpu[i].createInterruptController()
> system.cpu[i].interrupts.pio = ruby_port.master
> system.cpu[i].interrupts.int_master = ruby_port.slave
> system.cpu[i].interrupts.int_slave = ruby_port.master
>
> # Connect the cpu's cache ports to Ruby
> system.cpu[i].icache_port = ruby_port.slave
> system.cpu[i].dcache_port = ruby_port.slave
> else:
> system.system_port = system.membus.slave
> system.physmem.port = system.membus.master
> CacheConfig.config_cache(options, system)
> system.l2.prefetcher = StridePrefecher(degree = 3, latency =
> '10ns', size = 30)
>
> root = Root(full_system = False, system = system)
> Simulation.run(options, root, system, FutureClass)
>
>
> On 3/29/12, Mahmood Naderan <[email protected]> wrote:
>> currently I am using the old version. I am also stuck at the this point
>> i have not a successfull run with the latest version while enabling
>> the prefetcher.
>>
>> On 3/29/12, biswabandan panda <[email protected]> wrote:
>>> if possible send me your gem5 version in which it's running but the
>>> gem5
>>> is latest one.
>>>
>>> On Thu, Mar 29, 2012 at 11:38 AM, Mahmood Naderan
>>> <[email protected]>wrote:
>>>
>>>> i have to say the idea in that post doesn't work either
>>>>
>>>> On 3/29/12, Mahmood Naderan <[email protected]> wrote:
>>>> > the only information available is
>>>> > http://www.mail-archive.com/[email protected]/msg03370.html
>>>> >
>>>> > seems that no one has successfully configured yet.
>>>> >
>>>> > On 3/28/12, biswabandan panda <[email protected]> wrote:
>>>> >> Hi all,
>>>> >> how to configure the prefetcher in the latest gem5
>>>> >> version?
>>>> >>
>>>> >> --
>>>> >>
>>>> >> *thanks®ards
>>>> >> *
>>>> >> *BISWABANDAN*
>>>> >>
>>>> >
>>>> >
>>>> > --
>>>> > --
>>>> > // Naderan *Mahmood;
>>>> >
>>>>
>>>>
>>>> --
>>>> --
>>>> // Naderan *Mahmood;
>>>> _______________________________________________
>>>> gem5-users mailing list
>>>> [email protected]
>>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>>
>>>
>>>
>>>
>>> --
>>>
>>> *thanks®ards
>>> *
>>> *BISWABANDAN*
>>>
>>
>>
>> --
>> --
>> // Naderan *Mahmood;
>>
>
>
> --
> --
> // Naderan *Mahmood;
>
--
--
// Naderan *Mahmood;
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