Yes. That's the way all TLBs worked in M5, up until we added x86
support and needed a hardware page table walker for when there was a
TLB miss. Now all translations are instant except if the TLB needs the
CPU to wait while it handle a miss. The TLB is free to make the CPU
wait for other reasons if it wants, but the existing TLBs don't do that.
Gabe
Quoting Veydan Wu <[email protected]>:
Hi, all, I am running ALPHA programs on Gem5. Seems that the single TLB
request finishes immediately, the translateTiming() directly invokes
state->finish(), which returns true when the TLB request is not split. It
that correct? Does Gem5 assumes that there is no TLB access latency and the
physical address is immediately available? Thanks!
--
Regards,
Veydan
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
