Hi, When I simulate full system (gem5.debug), I got a assertion error, caused by "assert(!alreadyResponded);" in cache_impl.hh file. Thus I tried to debug with trace.
I find when a L2 cache forward the snoop packet to upper level (L1s), it didn't copy the memInhibit flag from the original packet to the forwarded packet. If the original packet has been responded by another L2 (memInhibit is set), and you don't forward that flag to upper level, how could you let upper level cache know data respond is needed (has been served)? This is my confusion after reading through the codes while I debug it. Please let me know if I make some misunderstand your codes. Thanks, Chao _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
