Perhaps a port scanner connected to the open port? Ali
On Apr 14, 2012, at 10:34 AM, Sathyanarayanan S wrote: > Thanks Andreas, > But I am new to gem5 simulator. Can you explain the procedure in detail? > > On Fri, Apr 13, 2012 at 1:47 PM, <[email protected]> wrote: > Send gem5-users mailing list submissions to > [email protected] > > To subscribe or unsubscribe via the World Wide Web, visit > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > or, via email, send a message with subject or body 'help' to > [email protected] > > You can reach the person managing the list at > [email protected] > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of gem5-users digest..." > > > Today's Topics: > > 1. Problems in running bbench ARM on gem5 (Sathyanarayanan S) > 2. Re: Problems in running bbench ARM on gem5 (Andreas Hansson) > 3. Re: Running multiple simulations simultaneously - for ARM FS > (Kirtika Ruchandani) > 4. L2 cache size in ARM model (Kirtika Ruchandani) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Fri, 13 Apr 2012 13:09:51 -0400 > From: Sathyanarayanan S <[email protected]> > To: [email protected] > Subject: [gem5-users] Problems in running bbench ARM on gem5 > Message-ID: > <CAE_juFzMv9KKsETeq=9mutk2ErbaiuM0brx=h4j-xdxwgaj...@mail.gmail.com> > Content-Type: text/plain; charset="utf-8" > > Hi, > I am running bbench simulation on arm_fs. The following message comes and > the simulation stops. I am not able to figure out the reason. > > /---- > > **** REAL SIMULATION **** > info: Entering event queue @ 0. Starting simulation... > warn: The clidr register always reports 0 caches. > warn: clidr LoUIS field of 0b001 to match current ARM implementations. > warn: The csselr register isn't implemented. > warn: instruction 'mcr bpiallis' unimplemented > warn: instruction 'mcr icialluis' unimplemented > warn: The ccsidr register isn't implemented and always reads as 0. > warn: instruction 'mcr dccimvac' unimplemented > warn: instruction 'mcr dccmvau' unimplemented > warn: instruction 'mcr icimvau' unimplemented > warn: instruction 'mcr bpiallis' unimplemented > warn: LCD dual screen mode not supported > warn: instruction 'mcr bpiallis' unimplemented > warn: instruction 'mcr icialluis' unimplemented > info: VNC client attached > info: VNC client detached > warn: Malformed protocol version ?`? > ` ?P? > panic: Vnc client not properly attached. > @ cycle 96494088946536 > [write:build/ARM_FS/base/vnc/vncserver.cc, line 317] > Memory Usage: 436560 KBytes > Program aborted at cycle 96494088946536 > Aborted > > > > ----/ > > Can anyone tell why this happens? > > -- > Regards, > Sathyanarayanan S > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: > <http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20120413/abd28c16/attachment-0001.html> > > ------------------------------ > > Message: 2 > Date: Fri, 13 Apr 2012 18:12:35 +0100 > From: Andreas Hansson <[email protected]> > To: gem5 users mailing list <[email protected]> > Subject: Re: [gem5-users] Problems in running bbench ARM on gem5 > Message-ID: > <[email protected]> > Content-Type: text/plain; charset="utf-8" > > What settings are you using? Try vncviewer -AutoSelect=0 -FullColor > -PreferredEncoding=raw :5900 > > From: [email protected] [mailto:[email protected]] On > Behalf Of Sathyanarayanan S > Sent: 13 April 2012 18:10 > To: [email protected] > Subject: [gem5-users] Problems in running bbench ARM on gem5 > > Hi, > I am running bbench simulation on arm_fs. The following message comes and the > simulation stops. I am not able to figure out the reason. > > /---- > > **** REAL SIMULATION **** > info: Entering event queue @ 0. Starting simulation... > warn: The clidr register always reports 0 caches. > warn: clidr LoUIS field of 0b001 to match current ARM implementations. > warn: The csselr register isn't implemented. > warn: instruction 'mcr bpiallis' unimplemented > warn: instruction 'mcr icialluis' unimplemented > warn: The ccsidr register isn't implemented and always reads as 0. > warn: instruction 'mcr dccimvac' unimplemented > warn: instruction 'mcr dccmvau' unimplemented > warn: instruction 'mcr icimvau' unimplemented > warn: instruction 'mcr bpiallis' unimplemented > warn: LCD dual screen mode not supported > warn: instruction 'mcr bpiallis' unimplemented > warn: instruction 'mcr icialluis' unimplemented > info: VNC client attached > info: VNC client detached > warn: Malformed protocol version ?`? > `?P? > panic: Vnc client not properly attached. > @ cycle 96494088946536 > [write:build/ARM_FS/base/vnc/vncserver.cc, line 317] > Memory Usage: 436560 KBytes > Program aborted at cycle 96494088946536 > Aborted > > > > ----/ > > Can anyone tell why this happens? > > -- > Regards, > Sathyanarayanan S > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: > <http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20120413/732aee2e/attachment-0001.html> > > ------------------------------ > > Message: 3 > Date: Fri, 13 Apr 2012 23:07:38 +0530 > From: Kirtika Ruchandani <[email protected]> > To: gem5 users mailing list <[email protected]> > Subject: Re: [gem5-users] Running multiple simulations simultaneously > - for ARM FS > Message-ID: > <ca+bork2s6oqqnx6yo0qrgsauguc1jmljegiqj_y62by_ndc...@mail.gmail.com> > Content-Type: text/plain; charset="iso-8859-1" > > @ Steve: Thank you, that was helpful. > Regards, > Kirtika > > > On Fri, Apr 13, 2012 at 4:49 AM, Steve Reinhardt <[email protected]> wrote: > > > The intention is that if you want to regularly vary parameters that aren't > > already exposed as command-line parameters, you should add command-line > > parameters that allow you to do that. Then you can compile a single binary > > and use a single config script and run your experiments just by changing > > the command lines. Note that you can change class parameters after your > > configuration is built (i.e., after the Python objects are instantiated) as > > long as you do it before m5.instantiate() is called to create the C++ > > objects. > > > > Steve > > > > > > On Thu, Apr 12, 2012 at 1:36 PM, Kirtika Ruchandani > > <[email protected]>wrote: > > > >> I was referring to the configs/common/ directory :). > >> From some previous experiments, I can see that the O3_ARM_v7a.py from > >> configs/common is being used. I just need multiple copies of this file with > >> different values for certain components. > >> Regards, > >> Kirtika > >> > >> > >> > >> On Fri, Apr 13, 2012 at 1:59 AM, Gabe Black <[email protected]>wrote: > >> > >>> ** > >>> You're not supposed to configure gem5 by changing the parameters in the > >>> src/ directory. You're supposed to write or use scripts from configs/ > >>> which > >>> instantiate the components of your simulation and configure instances of > >>> them there. The values in src/ are just the defaults. > >>> > >>> Gabe > >>> > >>> > >>> On 04/12/12 13:22, Kirtika Ruchandani wrote: > >>> > >>> Hi, > >>> I am trying to run multiple simulations simultaneously, and would like > >>> to do so out of the same gem5 folder. However, my CPU configuration > >>> differs > >>> in each simulation (prefetcher properties, branch predictors etc). Whats > >>> the best way to achieve this? > >>> I am considering making multiple copies of O3_ARM_v7a.py and tweaking > >>> the parameters I need to, one at a time. Only CacheConfig.py and > >>> Simulation.py seem to be using the O3_ARM_v7a.py and it would be easy to > >>> amend both these files (add more options similar to "arm_detailed" for > >>> cpu-type). > >>> Regards, > >>> Kirtika > >>> > >>> > >>> _______________________________________________ > >>> gem5-users mailing > >>> [email protected]http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > >>> > >>> > >>> > >>> _______________________________________________ > >>> gem5-users mailing list > >>> [email protected] > >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > >>> > >> > >> > >> > >> -- > >> -- > >> Kirtika Ruchandani > >> Final Year, Integrated BTech/MTech, > >> Comp. Sci & Engg, IIT Madras > >> > >> > >> > >> _______________________________________________ > >> gem5-users mailing list > >> [email protected] > >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > >> > > > > > > _______________________________________________ > > gem5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > > > -- > -- > Kirtika Ruchandani > Final Year, Integrated BTech/MTech, > Comp. Sci & Engg, IIT Madras > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: > <http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20120413/dfdc08a1/attachment-0001.html> > > ------------------------------ > > Message: 4 > Date: Fri, 13 Apr 2012 23:17:15 +0530 > From: Kirtika Ruchandani <[email protected]> > To: gem5 users mailing list <[email protected]> > Subject: [gem5-users] L2 cache size in ARM model > Message-ID: > <CA+boRk0913ATDLdO+ehNsDdcci706BKpHVfrPPH4=wpyl3m...@mail.gmail.com> > Content-Type: text/plain; charset="iso-8859-1" > > Hi, > I have a query about how the cache is configured in a full-system > simulation of an ARM cpu - > If your simulation uses fs.py like bbench, fs.py calls config_cache to set > up the cache which is defined in CacheConfig.py as follows: > > [snip] > def config_cache(options, system): > if options.l2cache: > if options.cpu_type == "arm_detailed": > system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = > options.l2_assoc, mshrs=16,tgts_per_mshr=8, > block_size=options.cacheline_size) > else: > system.l2 = L2Cache(size = options.l2_size, assoc = > options.l2_assoc, > [snip] > > I am wondering if this is wrong in the case where the user doesn't > explicitly specify the l2 size. the default l2 size is 2Mb (I forget where > that was defined). > The class O3_ARM_v7aL2 defines size to be 1 Mb, but that gets overwritten > here, since my config.ini shows 2Mb. > Am I missing something here? > Also, aren't both 1 Mb and 2Mb unrealistic sizes for the L2? I read > somewhere that the L2 cache size can be from 0 to 1Mb in a real system - > how often is it 1Mb ? Would be the performance drop be significant at > 256/512 Kb L2? > Regards, > Kirtika > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: > <http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20120413/cf9de1a2/attachment.html> > > ------------------------------ > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > End of gem5-users Digest, Vol 69, Issue 44 > ****************************************** > > > > -- > Regards, > Sathyanarayanan S > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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