Hi Amin, See inline.
On May 16, 2012, at 12:31 AM, Amin Farmahini wrote: > Hi All, > > I am trying to switch from an O3 core to a TimingSimple core using a pseudo > instruction. I would like to do a cpu switching when the O3 core sees a > specific pseudo instruction. Since that pseudo instruction could be anywhere > in the program (thus I don't know at what cycle I need to switch to the > TimingSimple core), I need to take care of switching using sys call emulation > and I cannot use the python script (right?). So I used the python script > (simulate.py) to write down my pseudo instruction. Below is a snippet of my > pseudo instruction: I think you can do it either way. You can have a pseudo instruction that just exists the simulation and have python see this, reconnect the system and restart it or you could try and build everything into code as you've done. I would argue that the prior is probably easier to get working. As you might have seen on the mailing list to get the prior working that have been some discussion and fixes on the mailing list recently. I don't think it's prefect yet, but it's a step in the right direction. Thanks, Ali > > ... > //getting pointer to old_cpu (this is O3) > BaseCPU *old_cpu = current_tc->getCpuPtr(); > //getting pointer to new_cpu (This is TimingSimple and is in idle condition) > BaseCPU *new_cpu = new_tc->getCpuPtr(); > > //draining old cpu. Do I need to drain the whole system? the other cpu is > idle. > old_cpu->drain(); > > //Switchout > old_cpu->switchOut(); > > //and the rest including takeOverFrom > .... > > However, I am getting the following assertion error when this pseudo > instruction is called. > gem5.debug: build/ARM/cpu/o3/mem_dep_unit_impl.hh:119: void > MemDepUnit<MemDepPred, Impl>::switchOut() [with MemDepPred = StoreSet, Impl = > O3CPUImpl]: Assertion `instList[0].empty()' failed. > > I found out other people had a similar problem and there is already a patch > for this (http://reviews.gem5.org/r/1092/). So I applied the patch, but I am > still getting the same assertion failure. So either I am doing something > wrong with my or may be the patch does not work fine. Any thoughts on that? > > My configuration: ARM, SE, one O3 and one TimingSimple in system, l2caches, > classic > > Thanks, > Amin > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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