Hi,
I'm running gem5 in SE mode for the ARM architecture. I'm using the
'arm_detailed' cpu type with --caches and --l2cache options activated.
However, all the statistics about the TLB (dtb and itb sections of the
statistics) are null:
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
...
(All the other stats seems to be ok)
Is the tlb not activated by default?
Is there a problem in the statistics count?
Regards.
Nathanaël Prémillieu
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