You wouldn't expect the O3CPU and Timing/Atomic to have exactly the same cache miss rate, for example, when the branch prediction is turned on in the O3 CPU, the i cache miss rate won't be the same, when it's out of order execution the d cache miss rate won't be the same. For timing and atomic differences, as memory access timings are difference, if you run an OS workload, which can affect scheduling.
On 1 Jun 2012, at 13:22, Ali chaker wrote: > Hi, > > I have run the same benchmark with the same HW configuration in ARM FS mode. > But I haven't the same cache miss statistics : > > for O3CPU : system.cpu.dcache.overall_miss_rate::cpu.data 0.021567 > # miss rate for overall accesses > system.cpu.icache.overall_miss_rate::cpu.inst 0.015336 > # miss rate for overall accesses > system.l2.overall_miss_rate::cpu.inst 0.011660 > # miss rate for overall accesses > system.l2.overall_miss_rate::cpu.data 0.040427 > # miss rate for overall accesses > > > for Timing : system.cpu.dcache.overall_miss_rate::cpu.data 0.006400 > # miss rate for overall accesses > system.cpu.icache.overall_miss_rate::cpu.inst 0.002485 > # miss rate for overall accesses > system.l2.overall_miss_rate::cpu.inst 0.007456 > # miss rate for overall accesses > system.l2.overall_miss_rate::cpu.data 0.034478 > # miss rate for overall accesses > > > for Atomic : system.cpu.dcache.overall_miss_rate::cpu.data 0.005185 > # miss rate for overall accesses > system.cpu.icache.overall_miss_rate::cpu.inst 0.001623 > # miss rate for overall accesses > system.l2.overall_miss_rate::cpu.inst 0.010589 > # miss rate for overall accesses > system.l2.overall_miss_rate::cpu.data 0.126456 > # miss rate for overall accesses > > Any help would be appreciated! Thanks! > > BR, ALI CHAKER > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
