Hi, All,
I am running SPEC CPU2000 benchmark in ARM FS mode.(ammp)
I copy ammp binary and input file to the /mnt of the disk image which
download from the gem5 website.
My .rcS file:
#!/bin/sh
/sbin/m5 checkpoint 0 0
/sbin/m5 checkpoint 100000000 200000000
/sbin/m5 loadsymbol
/sbin/m5 resetstats
< input
/sbin/m5 exit
The command line I used:
build/ARM_FS/gem5.opt --outdir=ammp00 --debug-flags=O3PipeView
--trace-start=50000 --trace-file=ammp_trace.out configs/example/fs.py
--num-cpus=4 --script=./configs/boot/ammp00.rcS
However the simulation just continue in 0.000367s and there is nothing
in the trace file.
The attachment is the stats.txt
Can anyone help to figure out the reason?
Is there something wrong in my rcS file?
Do I miss some important component?
Thanks in advance.
Regards,
Bojun Ma
---------- Begin Simulation Statistics ----------
sim_seconds 0.000367 #
Number of seconds simulated
sim_ticks 366614000 #
Number of ticks simulated
sim_freq 1000000000000 #
Frequency of simulated ticks
host_inst_rate 163144847 #
Simulator instruction rate (inst/s)
host_tick_rate 723554022 #
Simulator tick rate (ticks/s)
host_mem_usage 304836 #
Number of bytes of host memory used
host_seconds 0.51 #
Real time elapsed on the host
sim_insts 82659488 #
Number of instructions simulated
system.cf0.dma_read_full_pages 0 #
Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 #
Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 #
Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 #
Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 #
Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 #
Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 #
ITB inst hits
system.cpu0.dtb.inst_misses 0 #
ITB inst misses
system.cpu0.dtb.read_hits 30850 #
DTB read hits
system.cpu0.dtb.read_misses 89 #
DTB read misses
system.cpu0.dtb.write_hits 30956 #
DTB write hits
system.cpu0.dtb.write_misses 19 #
DTB write misses
system.cpu0.dtb.flush_tlb 0 #
Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 #
Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 53 #
Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 3 #
Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 63 #
Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 2 #
Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 8 #
Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 30939 #
DTB read accesses
system.cpu0.dtb.write_accesses 30975 #
DTB write accesses
system.cpu0.dtb.inst_accesses 0 #
ITB inst accesses
system.cpu0.dtb.hits 61806 #
DTB hits
system.cpu0.dtb.misses 108 #
DTB misses
system.cpu0.dtb.accesses 61914 #
DTB accesses
system.cpu0.itb.inst_hits 92632 #
ITB inst hits
system.cpu0.itb.inst_misses 52 #
ITB inst misses
system.cpu0.itb.read_hits 0 #
DTB read hits
system.cpu0.itb.read_misses 0 #
DTB read misses
system.cpu0.itb.write_hits 0 #
DTB write hits
system.cpu0.itb.write_misses 0 #
DTB write misses
system.cpu0.itb.flush_tlb 0 #
Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 #
Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 53 #
Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 3 #
Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 60 #
Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 #
Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 #
Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 #
Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 #
DTB read accesses
system.cpu0.itb.write_accesses 0 #
DTB write accesses
system.cpu0.itb.inst_accesses 92684 #
ITB inst accesses
system.cpu0.itb.hits 92632 #
DTB hits
system.cpu0.itb.misses 52 #
DTB misses
system.cpu0.itb.accesses 92684 #
DTB accesses
system.cpu0.numCycles 730422 #
number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 #
number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 #
number of work items this cpu completed
system.cpu0.num_insts 144095 #
Number of instructions executed
system.cpu0.num_int_alu_accesses 131129 #
Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 145 #
Number of float alu accesses
system.cpu0.num_func_calls 4371 #
number of times a function call or return occured
system.cpu0.num_conditional_control_insts 10824 #
number of instructions that are conditional controls
system.cpu0.num_int_insts 131129 #
number of integer instructions
system.cpu0.num_fp_insts 145 #
number of float instructions
system.cpu0.num_int_register_reads 660180 #
number of times the integer registers were read
system.cpu0.num_int_register_writes 122100 #
number of times the integer registers were written
system.cpu0.num_fp_register_reads 129 #
number of times the floating registers were read
system.cpu0.num_fp_register_writes 16 #
number of times the floating registers were written
system.cpu0.num_mem_refs 63567 #
number of memory refs
system.cpu0.num_load_insts 32054 #
Number of load instructions
system.cpu0.num_store_insts 31513 #
Number of store instructions
system.cpu0.num_idle_cycles 583456.136645 #
Number of idle cycles
system.cpu0.num_busy_cycles 146965.863355 #
Number of busy cycles
system.cpu0.not_idle_fraction 0.201207 #
Percentage of non-idle cycles
system.cpu0.idle_fraction 0.798793 #
Percentage of idle cycles
system.cpu0.kern.inst.arm 0 #
number of arm instructions executed
system.cpu0.kern.inst.quiesce 276 #
number of quiesce instructions executed
system.cpu1.dtb.inst_hits 0 #
ITB inst hits
system.cpu1.dtb.inst_misses 0 #
ITB inst misses
system.cpu1.dtb.read_hits 123098 #
DTB read hits
system.cpu1.dtb.read_misses 170 #
DTB read misses
system.cpu1.dtb.write_hits 88277 #
DTB write hits
system.cpu1.dtb.write_misses 37 #
DTB write misses
system.cpu1.dtb.flush_tlb 0 #
Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 #
Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 53 #
Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 3 #
Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 111 #
Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 12 #
Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 9 #
Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 123268 #
DTB read accesses
system.cpu1.dtb.write_accesses 88314 #
DTB write accesses
system.cpu1.dtb.inst_accesses 0 #
ITB inst accesses
system.cpu1.dtb.hits 211375 #
DTB hits
system.cpu1.dtb.misses 207 #
DTB misses
system.cpu1.dtb.accesses 211582 #
DTB accesses
system.cpu1.itb.inst_hits 461707 #
ITB inst hits
system.cpu1.itb.inst_misses 107 #
ITB inst misses
system.cpu1.itb.read_hits 0 #
DTB read hits
system.cpu1.itb.read_misses 0 #
DTB read misses
system.cpu1.itb.write_hits 0 #
DTB write hits
system.cpu1.itb.write_misses 0 #
DTB write misses
system.cpu1.itb.flush_tlb 0 #
Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 #
Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 53 #
Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 3 #
Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 57 #
Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 #
Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 #
Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 #
Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 #
DTB read accesses
system.cpu1.itb.write_accesses 0 #
DTB write accesses
system.cpu1.itb.inst_accesses 461814 #
ITB inst accesses
system.cpu1.itb.hits 461707 #
DTB hits
system.cpu1.itb.misses 107 #
DTB misses
system.cpu1.itb.accesses 461814 #
DTB accesses
system.cpu1.numCycles 732382 #
number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 #
number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 #
number of work items this cpu completed
system.cpu1.num_insts 588133 #
Number of instructions executed
system.cpu1.num_int_alu_accesses 513821 #
Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 145 #
Number of float alu accesses
system.cpu1.num_func_calls 17269 #
number of times a function call or return occured
system.cpu1.num_conditional_control_insts 54070 #
number of instructions that are conditional controls
system.cpu1.num_int_insts 513821 #
number of integer instructions
system.cpu1.num_fp_insts 145 #
number of float instructions
system.cpu1.num_int_register_reads 2627485 #
number of times the integer registers were read
system.cpu1.num_int_register_writes 554727 #
number of times the integer registers were written
system.cpu1.num_fp_register_reads 81 #
number of times the floating registers were read
system.cpu1.num_fp_register_writes 64 #
number of times the floating registers were written
system.cpu1.num_mem_refs 219505 #
number of memory refs
system.cpu1.num_load_insts 129130 #
Number of load instructions
system.cpu1.num_store_insts 90375 #
Number of store instructions
system.cpu1.num_idle_cycles 117695.737226 #
Number of idle cycles
system.cpu1.num_busy_cycles 614686.262774 #
Number of busy cycles
system.cpu1.not_idle_fraction 0.839297 #
Percentage of non-idle cycles
system.cpu1.idle_fraction 0.160703 #
Percentage of idle cycles
system.cpu1.kern.inst.arm 0 #
number of arm instructions executed
system.cpu1.kern.inst.quiesce 847 #
number of quiesce instructions executed
system.cpu2.dtb.inst_hits 0 #
ITB inst hits
system.cpu2.dtb.inst_misses 0 #
ITB inst misses
system.cpu2.dtb.read_hits 0 #
DTB read hits
system.cpu2.dtb.read_misses 0 #
DTB read misses
system.cpu2.dtb.write_hits 0 #
DTB write hits
system.cpu2.dtb.write_misses 0 #
DTB write misses
system.cpu2.dtb.flush_tlb 0 #
Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 0 #
Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid 53 #
Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 3 #
Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries 0 #
Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults 0 #
Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults 0 #
Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses 0 #
DTB read accesses
system.cpu2.dtb.write_accesses 0 #
DTB write accesses
system.cpu2.dtb.inst_accesses 0 #
ITB inst accesses
system.cpu2.dtb.hits 0 #
DTB hits
system.cpu2.dtb.misses 0 #
DTB misses
system.cpu2.dtb.accesses 0 #
DTB accesses
system.cpu2.itb.inst_hits 0 #
ITB inst hits
system.cpu2.itb.inst_misses 0 #
ITB inst misses
system.cpu2.itb.read_hits 0 #
DTB read hits
system.cpu2.itb.read_misses 0 #
DTB read misses
system.cpu2.itb.write_hits 0 #
DTB write hits
system.cpu2.itb.write_misses 0 #
DTB write misses
system.cpu2.itb.flush_tlb 0 #
Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 0 #
Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid 53 #
Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 3 #
Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries 0 #
Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 #
Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 #
Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults 0 #
Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 #
DTB read accesses
system.cpu2.itb.write_accesses 0 #
DTB write accesses
system.cpu2.itb.inst_accesses 0 #
ITB inst accesses
system.cpu2.itb.hits 0 #
DTB hits
system.cpu2.itb.misses 0 #
DTB misses
system.cpu2.itb.accesses 0 #
DTB accesses
system.cpu2.numCycles 0 #
number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 #
number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 #
number of work items this cpu completed
system.cpu2.num_insts 0 #
Number of instructions executed
system.cpu2.num_int_alu_accesses 0 #
Number of integer alu accesses
system.cpu2.num_fp_alu_accesses 0 #
Number of float alu accesses
system.cpu2.num_func_calls 0 #
number of times a function call or return occured
system.cpu2.num_conditional_control_insts 0 #
number of instructions that are conditional controls
system.cpu2.num_int_insts 0 #
number of integer instructions
system.cpu2.num_fp_insts 0 #
number of float instructions
system.cpu2.num_int_register_reads 0 #
number of times the integer registers were read
system.cpu2.num_int_register_writes 0 #
number of times the integer registers were written
system.cpu2.num_fp_register_reads 0 #
number of times the floating registers were read
system.cpu2.num_fp_register_writes 0 #
number of times the floating registers were written
system.cpu2.num_mem_refs 0 #
number of memory refs
system.cpu2.num_load_insts 0 #
Number of load instructions
system.cpu2.num_store_insts 0 #
Number of store instructions
system.cpu2.num_idle_cycles 0 #
Number of idle cycles
system.cpu2.num_busy_cycles 0 #
Number of busy cycles
system.cpu2.not_idle_fraction 0 #
Percentage of non-idle cycles
system.cpu2.idle_fraction 1 #
Percentage of idle cycles
system.cpu2.kern.inst.arm 0 #
number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 #
number of quiesce instructions executed
system.cpu3.dtb.inst_hits 0 #
ITB inst hits
system.cpu3.dtb.inst_misses 0 #
ITB inst misses
system.cpu3.dtb.read_hits 0 #
DTB read hits
system.cpu3.dtb.read_misses 0 #
DTB read misses
system.cpu3.dtb.write_hits 0 #
DTB write hits
system.cpu3.dtb.write_misses 0 #
DTB write misses
system.cpu3.dtb.flush_tlb 0 #
Number of times complete TLB was flushed
system.cpu3.dtb.flush_tlb_mva 0 #
Number of times TLB was flushed by MVA
system.cpu3.dtb.flush_tlb_mva_asid 53 #
Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid 3 #
Number of times TLB was flushed by ASID
system.cpu3.dtb.flush_entries 0 #
Number of entries that have been flushed from TLB
system.cpu3.dtb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu3.dtb.prefetch_faults 0 #
Number of TLB faults due to prefetch
system.cpu3.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
system.cpu3.dtb.perms_faults 0 #
Number of TLB faults due to permissions restrictions
system.cpu3.dtb.read_accesses 0 #
DTB read accesses
system.cpu3.dtb.write_accesses 0 #
DTB write accesses
system.cpu3.dtb.inst_accesses 0 #
ITB inst accesses
system.cpu3.dtb.hits 0 #
DTB hits
system.cpu3.dtb.misses 0 #
DTB misses
system.cpu3.dtb.accesses 0 #
DTB accesses
system.cpu3.itb.inst_hits 0 #
ITB inst hits
system.cpu3.itb.inst_misses 0 #
ITB inst misses
system.cpu3.itb.read_hits 0 #
DTB read hits
system.cpu3.itb.read_misses 0 #
DTB read misses
system.cpu3.itb.write_hits 0 #
DTB write hits
system.cpu3.itb.write_misses 0 #
DTB write misses
system.cpu3.itb.flush_tlb 0 #
Number of times complete TLB was flushed
system.cpu3.itb.flush_tlb_mva 0 #
Number of times TLB was flushed by MVA
system.cpu3.itb.flush_tlb_mva_asid 53 #
Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid 3 #
Number of times TLB was flushed by ASID
system.cpu3.itb.flush_entries 0 #
Number of entries that have been flushed from TLB
system.cpu3.itb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults 0 #
Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults 0 #
Number of TLB faults due to domain restrictions
system.cpu3.itb.perms_faults 0 #
Number of TLB faults due to permissions restrictions
system.cpu3.itb.read_accesses 0 #
DTB read accesses
system.cpu3.itb.write_accesses 0 #
DTB write accesses
system.cpu3.itb.inst_accesses 0 #
ITB inst accesses
system.cpu3.itb.hits 0 #
DTB hits
system.cpu3.itb.misses 0 #
DTB misses
system.cpu3.itb.accesses 0 #
DTB accesses
system.cpu3.numCycles 0 #
number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 #
number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 #
number of work items this cpu completed
system.cpu3.num_insts 0 #
Number of instructions executed
system.cpu3.num_int_alu_accesses 0 #
Number of integer alu accesses
system.cpu3.num_fp_alu_accesses 0 #
Number of float alu accesses
system.cpu3.num_func_calls 0 #
number of times a function call or return occured
system.cpu3.num_conditional_control_insts 0 #
number of instructions that are conditional controls
system.cpu3.num_int_insts 0 #
number of integer instructions
system.cpu3.num_fp_insts 0 #
number of float instructions
system.cpu3.num_int_register_reads 0 #
number of times the integer registers were read
system.cpu3.num_int_register_writes 0 #
number of times the integer registers were written
system.cpu3.num_fp_register_reads 0 #
number of times the floating registers were read
system.cpu3.num_fp_register_writes 0 #
number of times the floating registers were written
system.cpu3.num_mem_refs 0 #
number of memory refs
system.cpu3.num_load_insts 0 #
Number of load instructions
system.cpu3.num_store_insts 0 #
Number of store instructions
system.cpu3.num_idle_cycles 0 #
Number of idle cycles
system.cpu3.num_busy_cycles 0 #
Number of busy cycles
system.cpu3.not_idle_fraction 0 #
Percentage of non-idle cycles
system.cpu3.idle_fraction 1 #
Percentage of idle cycles
system.cpu3.kern.inst.arm 0 #
number of arm instructions executed
system.cpu3.kern.inst.quiesce 0 #
number of quiesce instructions executed
---------- End Simulation Statistics ----------
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