Thank you for a timely response, Jack. I have one additional question regarding the ASPLOS tutorial. In the tutorial with gcc_integrated benchmark, the tutorial shows the following command line:
m5.fast configs/example/se.py --bench=gcc_integrate --take-checkpoint=0 --simpoint It looks like we are taking the simpoint from the interval 0, yet in the ucsd: http://cseweb.ucsd.edu/~calder/simpoint/points/standard/spec2000-single-std-100M.html They show that the simpoint is taken at the interval 4 for the gcc_integrated workload. Is there any specific reason for taking it at the interval 0 or it was just 0 for an example purpose? Thank you. Jee Ho Ryoo 2012/6/21 Jack Harvard <[email protected]> > It's possible to run simpoint on any architecture, there's no reason > it should be architecture-dependent. > > Jack Harvard > > > On Wed, Jun 20, 2012 at 10:43 PM, Jee Ho Ryoo <[email protected]> wrote: > > Hi, > > > > In the ASPLOS tutorial, it says that the simpoint is only implemented in > > alpha. Has there been any progress in this towards ARM or X86 > architecture? > > Is it possible to run simpoint on either of two ISAs? Thank you. > > > > Jee Ho Ryoo > > > > _______________________________________________ > > gem5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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