Likely the entire instruction footprint fits in the L1 i cache and there is very little re-use on the data side. Removing the L2 probably lowers the access time to main memory by a substantial amount which improve performance.
Ali On 02.07.2012 20:06, Nyunyi Tshibangu wrote: > I am having hardtime understanding the number of cycles from SE mode statistcs > > 1)running with L1 only > build/X86/gem5.opt configs/example/se.py --cpu-type="detailed" --caches --maxinsts=10000000 --cmd=bzip2/bzip2 --options="bzip2/input.program" > I am getting number of cycles as: system.cpu.numCycles 54101855 > 2)running with L1/L2 caches > > build/X86/gem5.opt configs/example/se.py --cpu-type="detailed" --caches --l2cache --maxinsts=10000000 --cmd=bzip2/bzip2 --options="bzip2/input.program" > I am getting number of cycles as: system.cpu.numCycles 82713679 > does it make sense that performance get worse when adding L2 cache? why is ipc worse? am I looking at wrong info to determine instruction/cycles? > any idea? > Thanks > Marcus
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
