Thanks for the hint Ali. Going over the trace from instruction queue, I am almost positive it is a FloatAdd.
system.cpu0.fetch: [tid:0]: Instruction PC 0x8986 (0) created [sn:8792]. system.cpu0.fetch: [tid:0]: Instruction is: ldrneon8_uop.w system.cpu0.iq: Instruction is ready to issue, putting it onto the ready list, PC (0x8986=>0x898a).(0=>1) opclass:4 [sn:8792]. system.cpu0 T0 : 0x8986.0 : ldrneon8_uop.w : FloatAdd : D=0x00000000051319b0 A=0xbefffc18 12837500: system.cpu0: Removing committed instruction [tid:0] PC (0x8986=>0x898a).(0=>1) [sn:8792] ** opclass: 4 is defined as FloatAdd in src/cpu/op_class.hh. Thanks, Amin On Thu, Jul 26, 2012 at 8:36 PM, Ali Saidi <[email protected]> wrote: > ** > > > > > > On 26.07.2012 19:44, Amin Farmahini wrote: > > Hi, > > I'd like to change the latency of a couple of Neon instructions. I started > with VLD1 instruction which is called ldrNeon in Gem5. This instruction is > classified as a "FloatAdd" opClass. So I can modify the latency (opLat) of > "FloatAdd" class in O3_ARM_v7a.py file. However, this obviously changes the > latency of all instructions belong to FloatAdd which is not accepted. So I > think to change the latency of VLD1 instruction, I need to define a new > opClass for this instruction. Is this approach right? And if so, how can I > classify VLD1 under the new opClass? > I took a look at arch/arm/isa/insts/fp.isa and > arch/arm/isa/insts/macromem.isa to get some idea, but could find a way to > work around this. BTW, if there are any other ways to work around this, I'd > appreciate it if you could share it. > > Thanks, > Amin > > > > It doesn't seem like it's a floatAdd and it probably shouldn't be. Anyway, > your idea is correct and I think it's defined in > src/arch/arm/isa/insts/macromem.isa:688. > > iop = InstObjParams("vldsingle", "VldSingle", 'VldSingleOp', "", []) > > you should be abl eto change it to something like > > iop = InstObjParams("vldsingle", "VldSingle", 'VldSingleOp', {"op_class" > : "MyNewOpClass"}, []) > > > > Ali > > > > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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