Sure, Nilay. I will post the changes for review. And I will post those changes too that I made for lsq invalidations, I could not do that before as I got stuck with this ll/sc bug for last two weeks.
Thanks, Dibakar On 07/28/12, Nilay Vaish wrote: > On Fri, 27 Jul 2012, Dibakar Gope wrote: > > >So, the way I get past this issue is by clearing the locked flag in core 3's > >private cache when the invalidate hits the core 3 in line 15, that will > >ensure the core 3's store-conditional to fail and thus force it to > >loop/retry. I can post my changes made in the ruby side for review, if this > >looks ok. > > > > > > Your analysis seems correct to me. The transition from SM to IM state should > clear the locked bit since the cache lost the coherence permissions. Thanks > for tracking this down, and do post the changes to the review board. > > -- > Nilay _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
