On Mon, August 6, 2012 6:55 am, Ali chaker wrote: > Hi, > > > > I have a question regarding L2 Latency. Ive run the BBench benchmark with > 2MB L2 size and @600MHZ. when I used 30 ns and 34 ns L2 Latency it works > fine. But when I used 32ns or 35ns or 25ns Ive the following error (I > used > Cache debug flag). > > > > *anic: Uncachable load [sn:4304d08] PC (0xc016e0c0=>0xc016e0c4).(0=>1)* > > * @ cycle 983526217577* > > *[invoke:build/ARM/arch/generic/debugfaults.hh, line 94]* > > *Memory Usage: 532200 KBytes* > > *Program aborted at cycle 983526217577* > > */tmp/1343295426.694498: line 8: 16024 Aborted (core > dumped) $USER_STARTER* >
I would say that the problem may not be related to the latency of a cache access. It is just that the problem manifests itself when particular latencies are provided because everything got aligned for the problem to occur. I would suggest that you try to figure why this particular request was marked uncacheable, when the CPU is not expecting such requests. -- Nilay _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
