See Inline Hi, > I'm having some trouble understanding the following statistics in an > ARM SMP full system linux simulation (arm_detailed, n=2, from > gem5-stable) >
Best thing to do is grep around to see where these stats are used. > > numCycles : The test program is single threaded, with most activity on > CPU0. At the end of the test the stats.txt shows a different number > for switch_cpus0.numCycles than for switch_cpus1.numCycles. The > description would lead me to expect these to be identical. > This stat is incremented on every CPU tick(). If there are no tick event's scheduled for a CPU this stat won't be incremented. E.g., during kernel boot one core is busy loading the kernel while the other wait for an IPI to bring it up. It's not surprising that cpu1 is doing nothing if you're running a single threaded application. > > idleCycles / quiesceCycles : I don't quite follow the difference > between these statistics and how they map to the ARMv7 architecture. > Relationship to WFE/WFI ? > Yes, quiesce cycles are those spent waiting for an interrupt. Idle cycles are those spent waiting due to stalls, e.g., due to a cache miss, TLB miss, etc. > > Any help greatly appreciated! > > Regards, > Stuart. > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -Tony
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