Hi I did a test to see if shared last level cache misses for core X is separated from shared last level cache misses for core Y or the shared cache records the misses in a global manner. My finding shows that for this example: core 0: miss at A core 3: miss at B core 2: miss at C core 0: miss at D
then in the shared cache I see "A B C D". Is that correct? Isn't possible to save like this: (core 0, A) (core 3, B) (core 2, C) (core 0, D) Thanks for any comment -- Regards, Mahmood _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
