Line 79 is a macro inside of macmode.def. The real problem is inside rtl.c:
const unsigned HOST_WIDE_INT mode_mask_array[NUM_MACHINE_MODES] = {
#include "machmode.def"
};
But, I was incorrect, I was using the amd64 bit config. Using the amd32 bit
config works fine. I think the -DSPEC_CPU_Lp64 flag was casuing some
problems. But, similar codes is used throughout rtl.c so I don't know why
that specifically causes problems.
-Tony
On Thu, Sep 6, 2012 at 3:52 PM, Andreas Hansson <[email protected]>wrote:
> Hi Tony,
>
> Out of curiosity, what does it say on line 79? Is if just a matter of gcc
> 4.6 being more picky than the gcc42.cfg support offered?
>
> Andreas
>
> From: Anthony Gutierrez <[email protected]<mailto:[email protected]>>
> Reply-To: gem5 users mailing list <[email protected]<mailto:
> [email protected]>>
> Date: Thu, 6 Sep 2012 19:55:58 +0100
> To: gem5 users mailing list <[email protected]<mailto:
> [email protected]>>
> Subject: [gem5-users] Building SPEC 2006 gcc for ARM
>
> Hello,
>
> I know this isn't a gem5 question directly but I was hoping someone here
> could help out. I am trying to compile gcc from SPEC 2k6 for ARM. I am
> using CodeSourcery gcc version 4.6.3 (Sourcery CodeBench Lite 2012.03-57).
> I keep getting this error when trying to compile using runspec
> --config=arm.cfg --action=build --tune=base gcc:
>
> machmode.def:79:1: warning: left shift count >= width of type [enabled by
> default]
> machmode.def:79:1: error: initializer element is not constant
>
> My arm.cfg file is the Example-linux64-amd32-gcc42.cfg file with the
> compiler set to my ARM code sourcery compiler.
>
> Thanks,
> Tony
>
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