I've used private L2 caches with the classic memory model. You should only need to modify the CacheConfig.py file to create separate L2's and busses, then connect them to their respective cores and to the membus.
-Tony On Sun, Sep 30, 2012 at 3:41 PM, <[email protected]> wrote: > Hi All, > > I want to configure a system with multiple CPUs with private L1 and L2 > cache with classic memory (not RUBY). Also I don't want to have a shared > L3, so that means all L2 connect to the system memory bus. I've read this > thread > (http://www.mail-archive.com/**[email protected]/msg02588.**html<http://www.mail-archive.com/[email protected]/msg02588.html> > ). > > My question is 2 fold: > > 1) Do I simply change the (config/common/CacheConfig.py) file and create a > L2 for all the cores? or do I have to change coherency stuff as well? > > 2) The default coherency protocol is MI_example in classic memory model > right? so how does this configuration affect the coherency? I read on the > website that Private L1 and L2 is only supported for the MOESI_hammer > protocol. So do I have to use MOESI_hammer? and does it work with classic > memory model? > > Many Thanks > > > > ______________________________**_________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users<http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users> >
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