Pavlos

Thank you very much. I will try. Do you know about Instruction Cache(Icache)  
and Data Cache (Dcache) ? Please let me know later.

With many thanks
---
Musharaf

--- On Sun, 10/7/12, Pavlos Maniotis <ppmanio...@gmail.com> wrote:

From: Pavlos Maniotis <ppmanio...@gmail.com>
Subject: Re: [gem5-users] Cache Hit & Miss latencies
To: "gem5 users mailing list" <gem5-users@gem5.org>
Date: Sunday, October 7, 2012, 2:50 PM

Hi Musharaf,

I haven't found yet a way to set hit and miss latencies!
I am actually searching for this! Maybe by changing other
parameters such as clock etc.. will result in different latencies.
If you use ruby memory system you will see a ruby.stats file
in m5out directory with miss latencies after a simulation.

If I manage to find more infos I'll post back.

Hope this helps,

Pavlos

On Sun, 2012-10-07 at 11:36 -0700, Musharaf Hussain wrote:
> Hi Pavlos
> 
> If you don't mind can you sent me your instruction of command line
> please. I want to see hit and miss.
> 
> 
> Musharaf
>  
> 
> --- On Fri, 10/5/12, Pavlos Maniotis <ppmanio...@gmail.com> wrote:
>         
>         From: Pavlos Maniotis <ppmanio...@gmail.com>
>         Subject: Re: [gem5-users] Cache Hit & Miss latencies
>         To: "gem5 users mailing list" <gem5-users@gem5.org>
>         Date: Friday, October 5, 2012, 7:11 AM
>         
>         Thank you very much! Very helpful info!
>         
>         Pavlos 
>         
>         On Fri, 2012-10-05 at 09:35 -0400, Tao Zhang wrote:
>         > In configs/ruby/, there are several configuration files for
>         each 
>         > coherence protocol (i.e., MESI_CMP_directory.py). The cache
>         latency is 
>         > set in those files. Actually, the base class RubyCache has
>         several 
>         > latency parameters you can use(i.e., dataAccessLatency, 
>         > tagAccessLatency). See its definition in
>         src/mem/ruby/system/Cache.py 
>         > for the detail.
>         > 
>         > Tao
>         > 
>         > On 10/05/2012 09:27 AM, Pavlos Maniotis wrote:
>         > > Can somebody help me find where to set cache memory
>         parameters?
>         > > For the time I care about Hit&  Miss latencies etc...
>         > > I use ALPHA ISA in fs mode and I run the splash2
>         benchmarks
>         > > with ruby memory system.
>         > >
>         > >
>         > > Thanks in advance!
>         > >
>         > > Pavlos
>         > >
>         > > _______________________________________________
>         > > gem5-users mailing list
>         > > gem5-users@gem5.org
>         > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>         > _______________________________________________
>         > gem5-users mailing list
>         > gem5-users@gem5.org
>         > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>         
>         
>         _______________________________________________
>         gem5-users mailing list
>         gem5-users@gem5.org
>         http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>         
> _______________________________________________
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Reply via email to