Hi All, In O3 LSQ, when a load packet is not accpeted by L1D (i.e., sendTimingReq() returns false), the pipeline is restarted and the load and all younger instructions are squashed. This causes a lot of instruction squashes when the processor is wide or when cache has a limited number of MSHRs. I don't understand why it is needed to sqaush instructions? We can instead save the retry packet and send the retry packet when LSQ is triggered by recvRetry() function. We do this for store packets, and I believe the same mechansim can be used for load instructions as well. Any thoughts on that?
Thanks, Amin
_______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
