On Wed, 2012-11-21 at 12:15 -0600, Nilay Vaish wrote: > On Wed, 21 Nov 2012, Pavlos Maniotis wrote: > > > Hello everyone, > > > > I am trying to simulate a system with 4 cpus and > > one shared L1 cache (cache shared among cpus). > > I tried to modify MESI_CMP_directory.py in > > /gem5/configs/ruby by changing this code: > > (I actually removed the "for" command and replaced i with 0 - > > the idea was to create only one L1 cache) > > > > and I have deleted the code that creates the L2 caches. > > > > The problem is that I get errors when I try to run simulations. > > > > > > It would be thankful if someone could help me to understand > > what is going wrong and how I could get L1 shared cache working. > > > > You will have to write a new protocol or modify an existing to do such a > thing. MESI CMP directory protocol has two levels of caching and you can > not do away with one of the levels just by deleting the python code. > Instead you might want to set the size of l1 cache so small that all the > accesses to the l1 cache end up in a miss. > > -- > Nilay
Thank you very much Nilay, I think that the "trick" with the small L1 cache (with 0 latency) would be a great solution compared to writing again a new protocol. Thanks again, Pavlos PS: other ideas are also welcome! _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
