It does make sense to include ports into the tlbs to communicate between
them if I want to model the message passing? Or it would be a better
approach to use the ports on the CPUs?
I understood that the ports are there to communicate MemObjects with the
memory through the (network? a bus?), but TLBs are not MemObjects, the
pageWalker is (because it have to access the memory to do the walk). So
it won't make sense to include those ports in the TLB?
How CPUs communicate each other? I'm not really asking for an
explanation, but to see if someone can point out where to look in the
code. I'm using the arm_detailed processor.
I'm absolutely messed up with this as you can see...
Thank you!
On Mon, 19 Nov 2012, Albert wrote:
Ok, found and written a possible solution to this. I appreciate the
help because I would continued searching it from a python point of
view. Now I'm able to retrieve a pointer to others' TLBs and make a
lookup. But I also want to emulate a delay meaning the time that
would take to send the request to the TLBs and receive the reponse
from each one. Taking into account that this would be a broadcast,
the time can be fixed. How can it be done properly?
This would require a much more detailed design as to how this
communication is happening, what other events is it overlapped with. I
think you should try to understand how the tlb structure works in gem5
and add the latency as you think it should be.
--
Nilay
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