On 11/24/2012 10:00 PM, Nilay Vaish wrote:
On Sat, 24 Nov 2012, zhengchl wrote:
Hi,
I implement a 1 level cache coherence protocol based on
MOESI-CMP-directory, and my protocol passes Ruby_random_test with max
16 cores and 10000000 loads. But I'm not sure those testes are
enough, what should I do next to verify a protocol?
You can go through the literature on verification of coherence
protocols and apply the techniques people have devised. I think the
random tester is the best you can do as far as gem5 is concerned. You
might want to test your protocol with some workloads as well.
--
Nilay
Thank you!
I'm curious about DMA transition when directory in M/O state sees a
DMA_WRITE event, this code is copied from MOESI_CMP_directory-dir.sm.
1. transition({O,M}, DMA_WRITE, OI_D) {
2. f_forwardRequestDirIsRequestor; // need the modified data
before we can proceed
3. g_sendInvalidations; // these go to the DMA
Controller
4. v_allocateTBE;
5. i_popIncomingRequestQueue;
6. }
7. transition(OI_D, Data, XI_U) {
8. qw_queueMemoryWBRequest;
9. a_sendDMAAck2; // ack count may be zero
10. p_writeFwdDataToMemory;
11. l_writeDMADataToMemoryFromTBE;
12. w_deallocateTBE;
13. j_popIncomingUnblockQueue;
14. }
15. transition(XI_U, Exclusive_Unblock, I) {
16. cc_clearSharers;
17. c_clearOwner;
18. j_popIncomingUnblockQueue;
19. }
Question 1. in line 3 and line 17, directory send Inv message to all his
sharers but not owner (however, owner must be in state MM, M, or O,
these state can't receive a Inv message), and then transfer to I state.
But, cache in MM, M or O state haven't be invalidated. This is incoherence.
Question 2. line 10 and 11 write data from DMA to tbe of directory,
while line 8 write data from cache to memory. This is unable to understand.
Question 3. Ruby_Random_Test just test request from cores, is there any
tester to check request from DMA?
Thank you!
--
Chuanlei Zheng
Department of Computer Science and Technology
Nanjing University
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
