Set both the number of MSHRs and the number of targets per MSHR to 1. If you ONLY set the number of MSHRs to one, then you could have multiple outstanding misses to the same cache line.
Amin On Sat, Nov 24, 2012 at 3:30 PM, Nilay Vaish <[email protected]> wrote: > On Sat, 24 Nov 2012, pushkar nandkar wrote: > > Hi, >> >> Currently the classic memory system has a non-blocking cache which is >> handled using MSHR and Write Buffer. >> I want to implement a blocking cache and measure time/clock ticks for >> which >> the CPU stalled. I am implementing a multicore system here. >> >> Is there a way to implement that, like disabling the MSHR functionality >> which handles the non-blocking access? >> >> I parsed the files related in the *src/mem/cache/* *but could not get >> which >> >> part of the code will help to implement that. >> >> Has anyone implemented it(blocking cache)? >> >> Any clues/ideas to implement that will be really helpful! >> >> > Why not set the number of mshrs to 1? That way only one miss can be > outstanding at a time. > > -- > Nilay > ______________________________**_________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users<http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users> >
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