On Mon, 26 Nov 2012, Roberto Rodríguez-Rodríguez wrote:
Hello everyone,
I need to create a model with cpus, L1i, L1d and L2 private and shared L3.
As example I am using the file configs/ruby/MOESI_CMP_directory.py, these
file depends of src/mem/protocol/(MOESI_CMP_directory-dir.sm,
MOESI_CMP_directory-L1cache.sm and MOESI_CMP_directory-L2cache.sm) among
others files.
Could anybody tell me if for the structure, I have to use, I have to define a
new MOESI_CMP_directory-*L3*cache.sm? or is there an easy way to define the
structure I have to use?
I think adding a new level of cache requires adding a new controller type.
Or else you can modify one of the existing levels to include a new level
(like the MOESI hammer protocol which has two levels under the same
controller).
--
Nilay
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