On Fri, 30 Nov 2012, hanfeng QIN wrote:
I apologize for my carelessness, Nilay. I am sorry to say that I still can
not prevent the error even I revert the patch. To make you understand my
simulation flow, I list my process as following.
Step 1: I made a checkpoint using TimingSimple CPU type.
$build/ALPHA_MESI_CMP_directory/gem5.opt -d ../exp/2012-11-30-ruby_ckpt
configs/example/se.py -n 2 --caches --l1d_size=32kB --l1d_assoc=2
--l1i_size=32kB --l1i_assoc=2 --l2cache --l2_size=4MB --l2_assoc=8
--num-l2caches=1 -c
../app/mcf_base.alphaev67-gcc44-nn;../app/bzip2_base.alphaev67-gcc44-nn -o
../app/inp.in > inp.out 2>> inp.err;../app/input.program 10 >
input.program.out 2>> input.program.err *-I 50000000 --checkpoint-at-end
--cpu-type=timing*
Step 2: I restored from the checkpoint using TimingSimple CPU type and after
cache warmed up then switch to O3 cpu type for detailed measurement.
$build/ALPHA_MESI_CMP_directory/gem5.opt -d ../exp/2012-11-30-ruby_ckpt
--stats-file=stats.ruby configs/example/se.py -n 2 --caches --l1d_size=32kB
--l1d_assoc=2 --l1i_size=32kB --l1i_assoc=2 --l2cache --l2_size=4MB
--l2_assoc=8 --num-l2caches=1 -c
../app/mcf_base.alphaev67-gcc44-nn;../app/bzip2_base.alphaev67-gcc44-nn -o
../app/inp.in > inp.out 2>> inp.err;../app/input.program 10 >
input.program.out 2>> input.program.err *-I 100000000 --ruby -W 20000
--restore-with-cpu=timing --cpu-type=timing -r 1 -s 1*
As I mentioned previously, if '-s' not specified, '-W' does not work
according to config/common/simulation.py script. However, in this case, the
errors occurred again.
Global frequency set at 1000000000000 ticks per second
warn: CoherentBus system.membus has no snooping ports attached!
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
warn: optional parameter system.cpu0.workload:M5_pid not present
warn: optional parameter system.cpu1.workload:M5_pid not present
info: Entering event queue @ 75224531000. Starting simulation...
hack: be nice to actually delete the event here
Switched CPUS @ tick 75224587000
Changing memory mode to timing
System already in target mode. Memory mode unchanged.
switching cpus
gem5.opt: build/ALPHA_MESI_CMP_directory/cpu/simple/timing.cc:157: virtual
void TimingSimpleCPU::switchOut(): Assertion `_status ==
BaseSimpleCPU::Running || _status == Idle' failed.
Program aborted at cycle 75224587000
I am not ready to believe that you made the change I asked you to make. In
fact, it seems that you have made additional changes to the file
configs/common/Simulation.py as one of the print statements (line 438) is
missing from the output you posted.
--
Nilay
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