Is this true that there is a traffic generator? I cannot find this in /src/cpu/testers. Instead, there is some kinds of test code. Are these traffic generators? Additionally, do you know how to connect these test object?
-----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of Andreas Hansson Sent: Thursday, December 13, 2012 11:46 PM To: gem5 users mailing list Subject: Re: [gem5-users] how to connect dummy device Use the traffic generator in src/cpu/testers/traffic_gen. You can get it to send periodic requests with the LINEAR state. Andreas On 13/12/2012 14:40, "mjkim" <[email protected]> wrote: >Thank you for reply. >I also made a dummy object based from CommMonitor. >But, the result was same. >There certainly need not slave port. >I want to focus on the master port and send a memory request >periodically to the main memory. >Somebody help me plz... >Thank you. > >-----Original Message----- >From: [email protected] [mailto:[email protected]] >On Behalf Of Andreas Hansson >Sent: Thursday, December 13, 2012 11:33 PM >To: gem5 users mailing list >Subject: Re: [gem5-users] how to connect dummy device > >The connections look reasonable. I would suggest to start with e.g. the >CommMonitor if you want a simpler starting point. > >Why does your dummy object need both a master and a slave port? > >Andreas > >From: mjkim ><[email protected]<mailto:[email protected]>> >Reply-To: gem5 users mailing list ><[email protected]<mailto:[email protected]>> >Date: Thursday, 13 December 2012 14:18 >To: "[email protected]<mailto:[email protected]>" ><[email protected]<mailto:[email protected]>> >Subject: Re: [gem5-users] how to connect dummy device > >I wanna make the dummy device for some experiments. >I made a dummy object from cache-object based function. >However, after built a gem5, simulation is not running. >I connected the port like follow. (in the FSConfig.py) > >System.dummy = Dummy() >System.dummy.mem_side = system.membus.slave System.dummy.cpu_side = >system.membus.master > >And I also tried like, > >System.dummy = Dummy() >System.todummybus = CoherentBus() >System.dummy.mem_side = system.membus.slave System.dummy.cpu_side = >system.todummybus.master > >These configuration make the segmentation fault. >Please someone help me for solving this problem. Thank you. > >-- IMPORTANT NOTICE: The contents of this email and any attachments are >confidential and may also be privileged. If you are not the intended >recipient, please notify the sender immediately and do not disclose the >contents to any other person, use it for any purpose, or store or copy >the information in any medium. Thank you. > >_______________________________________________ >gem5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > >_______________________________________________ >gem5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
