On Fri, Dec 21, 2012 at 11:56 AM, Nilay Vaish <[email protected]> wrote:
> On Fri, 21 Dec 2012, Xin Tong wrote:
>
>> Hi
>>
>> Does gem5 implement a TLB for x86 O3 processor ?
>>
>
> Yes.
>
I am reading how TLB is simulated in FS mode. As shown below. it seems
that if a TLB miss happens. The pagewalker is invoked and if the page
walker does not hit a fault. The translation is considered to be
finished ( i.e. delayedResponse is not set to true ).
does that mean the TLB hit takes on cycles ?
TlbEntry *entry = lookup(vaddr);
if (!entry) {
if (FullSystem) {
// XIN. This is where the xlation fails and the
walker starts.
Fault fault = walker->start(tc, translation, req, mode);
if (timing || fault != NoFault) {
// This gets ignored in atomic mode.
delayedResponse = true;
return fault;
}
entry = lookup(vaddr);
assert(entry);
Xin
> --
> Nilay
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