It's X86 FS and classic model.

Jinchun Kim

On Jan 7, 2013, at 4:17 PM, Nilay Vaish <ni...@cs.wisc.edu> wrote:

> On Mon, 7 Jan 2013, Jinchun Kim wrote:
> 
>> I was printing out TLB entries whenever virtual address hit or miss on TLB.
>> And I found that TLB miss occurs even though TLB already has matched entry
>> in it.
>> 
>> For example,
>> 4949665272500: system.cpu.dtb: L1 TLB Miss : VA = 0x7fab3f32c280
>> 4949665272500: system.cpu.dtb: tlb[41] : VPN = 0x7fab3f32c000, PPN =
>> 0x1facd000
>> 
>> Translation for VA = 0x7fab3f32c280 is already in tlb[41].
>> However, it is considered as miss.
>> After this weird TLB miss, gem5 puts same translation in TLB again.
>> 
>> 4949667892500: system.cpu.dtb: tlb[41] : VPN = 0x7fab3f32c000, PPN =
>> 0x1facd000
>> 4949667892500: system.cpu.dtb: tlb[42] : VPN = 0x7fab3f32c000, PPN =
>> 0x1facd000
>> ...........(abbreviated)
>> 4949667892500: system.cpu.dtb: tlb[46] : VPN = 0x6b4000, PPN = 0x1ff27000
>> 4949667892500: system.cpu.dtb: tlb[47] : VPN = 0x6b4000, PPN = 0x1ff27000
>> 4949667892500: system.cpu.dtb: tlb[48] : VPN = 0x6bd000, PPN = 0x1ff0a000
>> 4949667892500: system.cpu.dtb: tlb[49] : VPN = 0x6bd000, PPN = 0x1ff0a000
>> 
>> As you can see, there are several same translations in TLB.
>> I played with this simulation with latest gem5-stable and dev version.
>> Does anyone have idea why this is happening?
>> I just don't understand why gem5 can't find proper translation when it is
>> already in TLB and put same translation again.
> 
> Which architecture?
> 
> --
> Nilay
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