Hi Andreas,

I am not sure if you have added the tFAW and tRRD in SimpleDRAM. I saw the
slides on MICRO tutorial that tFAW had been completed but I didn't find any
change in the latest code. 

Regards,

-Tao

-----Original Message-----
From: [email protected] [mailto:[email protected]] On
Behalf Of Andreas Hansson
Sent: Tuesday, January 08, 2013 1:48 AM
To: gem5 users mailing list
Subject: Re: [gem5-users] DRAMSim2 Patch--deleted link

If you want a cycle accurate DDR interface, then DRAMSim2 is probably the
way to go. Please remember though that there is nothing "cycle accurate"
about the controller model in DRAMSim2, so the question is what it really
gives you. I would argue that there is a distinction to be made between
accuracy and precision, but perhaps that's just me :-)

The SimpleDRAM model in gem5 is far more general (and much faster) as it
attempts to be a truthful representation of the controller, but only models
the DRAM by means of timings.

If you really care about the cycle-level DRAM behaviour, I would even
suggest getting traces out of gem5 (the CommMonitor can do this for you) and
then replay them on an RTL implementation of a real DRAM controller.

Andreas

From: Mansour Shafaei Moghaddam
<[email protected]<mailto:[email protected]>>
Reply-To: gem5 users mailing list
<[email protected]<mailto:[email protected]>>
Date: Monday, 7 January 2013 22:23
To: "[email protected]<mailto:[email protected]>"
<[email protected]<mailto:[email protected]>>
Subject: Re: [gem5-users] DRAMSim2 Patch--deleted link

@Ben: forgot to answer your question!! I want to study the cycle accurate
behavior of memory. As far as I know, there is no support for such a thing
inside the gem5 itself.

On Mon, Jan 7, 2013 at 5:20 PM, Mansour Shafaei Moghaddam
<[email protected]<mailto:[email protected]>> wrote:
@Ben: Thank for the links, Ben. Actually I had seen those but I had not
tried them. They look rather old, so, I thought that Tao's patch must be
better.
@Tao: Thanks for your quick response. Is the issue technical?


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