Hi Tao, Thanks for your quick reply. I use the command like this:
./build/ALPHA/gem5.opt --dump-config=debug.ini --stats-file=a.txt configs/example/se-cmp.py --num-cpus=1 --caches --l2cache --num-dirs=1 -cpu-type=detailed --benchmark=bzip2 In my case, although simpleDRAM called SimpleDRAM::recvAtomic(PacketPtr pkt), the functionality works, leaving only imprecise timing calculation. Could you please confirm that, your SimpleDRAM really calls the timing caculation functions like *SimpleDRAM::doDRAMAccess(DRAMPacket* dram_pkt) or SimpleDRAM::estimateLatency(DRAMPacket* dram_pkt, Tick inTime) *in Simple_dram.cc file? I was running in GDB mode and make breakpoints in simple_dram.cc : doDRAMAccess function, but after a long simulation, the simulation was not halted, which means that the simulation never called doDRAMAccess function. Regards, Shuchang 2013/1/10 Tao Zhang <[email protected]> > Hi Shuchang,**** > > ** ** > > Did you fast-forward any instructions? If so, the atomicCPU will be used > during the fastforward. **** > > In my case, the SimpleDRAM works well. **** > > ** ** > > -Tao**** > > ** ** > > *From:* [email protected] [mailto:[email protected]] *On > Behalf Of *单书畅 > *Sent:* Wednesday, January 09, 2013 10:56 PM > *To:* [email protected] > *Subject:* [gem5-users] question about simpleDRAM**** > > ** ** > > Hi all,**** > > ** ** > > It seems that the simple DRAM is built upon abstract_memory to simulate > the memory timing more accurately. I found that there are two DRAM timing > functions namely SimpleDRAM::recvAtomic(PacketPtr pkt) > and SimpleDRAM::recvTimingReq(PacketPtr pkt).**** > > ** ** > > More precisely, the recvAtomic function simply calculates the latency like > this: **** > > ** ** > > Tick**** > > SimpleDRAM::recvAtomic(PacketPtr pkt)**** > > {**** > > DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), > pkt->getAddr());**** > > ** ** > > // do the actual memory access and turn the packet into a response**** > > access(pkt);**** > > ** ** > > Tick latency = 0;**** > > if (!pkt->memInhibitAsserted() && pkt->hasData()) {**** > > // this value is not supposed to be accurate, just enough to**** > > // keep things going, mimic a closed page**** > > latency = tRP + tRCD + tCL;**** > > }**** > > return latency;**** > > }**** > > ** ** > > It would *NOT* call *SimpleDRAM::doDRAMAccess(DRAMPacket* dram_pkt) *which > simulates the DRAM module functionality. (Actually* SimpleDRAM::recvTimingReq > *does it*)***** > > ** ** > > *The problem is, when I run gem5 in detailed mode, I found that > *SimpleDRAM::recvAtomic > is called rather than *SimpleDRAM::recvTimingReq.***** > > ** ** > > Am I missing anything here? **** > > ** ** > > ** ** > > Regards,**** > > shuchang**** > > ** ** > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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