My suggestion for debugging this is to use debug tracing to see how you got there. Since you know when the error happens, you can turn on tracing just a little bit in advance so you're not slowing down the whole simulation. So add soemthing like:
--trace-start=5065359000000 --debug-flag=TLB,Ruby --trace-file=trace.out and then look at the output, starting from the end, and see if it shows how you got there. Those might not be the best (or even the correct) debug flags, I'm just doing this off the top of my head. Steve On Fri, Jan 11, 2013 at 5:22 AM, Mostafa Mahmoud Hassan < mostafa.m.has...@hotmail.com> wrote: > Then, how could I trace the TLB translations ?? > and another question is : why this problem occurs only when I try to run > the benchmark, i.e. If I just booted the system without launching a > benchmark (no benchmark .rcs file passed in command line) , no errors > occur. Could the compilation of the benchmark be the root cause ?? > > Mostafa > > > Date: Thu, 10 Jan 2013 19:31:28 -0600 > > From: ni...@cs.wisc.edu > > To: mostafa.m.has...@hotmail.com > > CC: gem5-users@gem5.org > > Subject: RE: [gem5-users] Running benchmark on FS X86 : Assertion > `!delayedResponse' failed. > > > > On Fri, 11 Jan 2013, Mostafa Mahmoud Hassan wrote: > > > > > > > > I could not figure out what is the problem in the first place. All > what > > > I can see is that the code behavior seems illogical because it will > > > certainly cause the assertion to fail consistently in timing mode > &g t; > > > > > > If the code that you are claiming is incorrect, it seems not a single > > translation would happen. Why don't you test your theory to check if > that > > is the case? > > > > -- > > Nilay > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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