Prior to some changes that will be committed soon it was possible for a CPU to stop in the middle of a micro-op for a checkpoint. Some changes on the review board change this functionality so it will only stop at instruction boundaries.
Ali On 15.01.2013 14:33, Anouk wrote: > Dear, > > I have a question about checkpointing. > Is it possible that a instruction can be fetched before the ROI (before the > checkpoint is taken) and completed after the checkpoint? And if so, could you > please give me a hint where I could find this in the checkpoint file (m5.cpt) or > somewhere else? > > The reason I am asking this, is because of some traces I made about instruction > fetching in X86. I found that when restoring from a checkpoint, it is possible > to have, as the first line in such a trace, the completion of an instruction > fetch (without any mention of the start of the instruction fetch). > This made me wonder if such a thing is possible and how information about the > start of the instruction fetch (before ROI) would be passed to the CPU/ITB to > complete the instruction fetch in the ROI. > > Thank you very much, > Kind regards, > Anouk > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1] Links: ------ [1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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