Hi Orangeade, What about the misses per thousand instructions (E.g. device MSHR misses by instructions) for both models?
Ali On Jan 22, 2013, at 6:59 AM, Mr. Orangeade <[email protected]> wrote: > Hi guys, > > I'm trying to compare the values of the cache-related counters for the > functional and performance models and observing strange difference I can't > explain. > I'm running not-time-related benchmark and got the following values: > > First row -- values for a functional model > Second row -- values for a performance model (arm_detailed) > > L1I-misses: 8369552 / 9982538 (+19%) > L1D-misses: 10526355 / 37332430 (+350%) > L2(I)-misses: 516328 / 624030 (+20%) > L2(D)-misses: 3610866 / 3626699 (+0.4%) > > L1I/L2(I)/L2(D) values look good to me. > We see slightly bigger values due to a speculative execution. > But the value for L1D is too big to be correct. > > One potential explanation is the fact that multiple sequential accesses to > the same cache line are treated as different misses by performance model > until the data come from the next level cache. > Does it sound correct? > > Thanks > Orangeade > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
