I didn't read your entire email, but at first glance I noticed that you have two l2caches for a cpu and both are connected to the same master and slave port.
Thanks, Amin On Wed, Jan 23, 2013 at 7:32 PM, Rodrigo Reynolds Ramírez < [email protected]> wrote: > > Hello everyone: > > I need to implement an architecture similar to Intel i7 (private L1 and L2 > and a shared L3). I am using the classic memory model. I changed the files > Caches.py, CacheConfig.py and Options, I followed the instructions showed > in the forum. My I idea is to have the possibility of use the system I > want or the actual system (private L1 and shared L2), and control the > system to use from the command line. > > The actual system works great, but I have a problem with the system with > L3, I got this error message: > > :$ build/X86/gem5.opt configs/example/se.py --caches --l1d_size=32kB > --l1i_size=32kB --l2_size=256kB --l3cache --l3_size=1MB -c > tests/test-progs/hello/bin/x86/linux/hello > gem5 Simulator System. http://gem5.org > gem5 is copyrighted software; use the --copyright option for details. > gem5 compiled Jan 24 2013 01:15:35 > gem5 started Jan 24 2013 02:20:38 > gem5 executing on mulhacen > command line: build/X86/gem5.opt configs/example/se.py --caches > --l1d_size=32kB --l1i_size=32kB --l2_size=256kB --l3cache --l3_size=1MB -c > tests/test-progs/hello/bin/x86/linux/hello > warning: add_child('l2cache'): child 'l2' already has parent > Global frequency set at 1000000000000 ticks per second > 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 > gem5.opt: build/X86/base/statistics.hh:983: void > Stats::VectorBase<Derived, Stor>::doInit(Stats::size_type) [with Derived = > Stats::Vector, Stor = Stats::StatStor, Stats::size_type = unsigned int]: > Assertion `!storage && "already initialized"' failed. > Program aborted at cycle 0 > Aborted (core dumped) > > I checked the config.ini (using the config.dot.pdf) and all the > connections seem to be ok. I am forgetting something? I copy below the > contents of the modified files and config.ini. > > Thanks in advance, > Rodrigo > > *Options.py:* I add this new option > parser.add_option("--l3cache", action="store_true") > > *Caches.py:* I add the L3 cache > class L3Cache(BaseCache): > assoc = 8 > block_size = 64 > latency = '30ns' > mshrs = 20 > tgts_per_mshr = 12 > > > *CacheConfig.py: *The main changes were done here > > import m5 > from m5.objects import * > from Caches import * > from O3_ARM_v7a import * > > def config_cache(options, system): > > if options.l3cache: > if options.cpu_type == "arm_detailed": > system.l3 = O3_ARM_v7aL3(size = options.l3_size, assoc = > options.l3_assoc, > block_size=options.cacheline_size) > else: > system.l3 = L3Cache(size = options.l3_size, assoc = > options.l3_assoc, > block_size=options.cacheline_size) > > system.tol3bus = CoherentBus() > system.l3.cpu_side = system.tol3bus.master > system.l3.mem_side = system.membus.slave > > else: > if options.l2cache: > if options.cpu_type == "arm_detailed": > system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = > options.l2_assoc, > block_size=options.cacheline_size) > else: > system.l2 = L2Cache(size = options.l2_size, assoc = > options.l2_assoc, > > block_size=options.cacheline_size) > > system.tol2bus = CoherentBus() > system.l2.cpu_side = system.tol2bus.master > system.l2.mem_side = system.membus.slave > > for i in xrange(options.num_cpus): > if options.caches: > if options.cpu_type == "arm_detailed": > icache = O3_ARM_v7a_ICache(size = options.l1i_size, > assoc = options.l1i_assoc, > block_size=options.cacheline_size) > dcache = O3_ARM_v7a_DCache(size = options.l1d_size, > assoc = options.l1d_assoc, > block_size=options.cacheline_size) > else: > icache = L1Cache(size = options.l1i_size, > assoc = options.l1i_assoc, > block_size=options.cacheline_size) > dcache = L1Cache(size = options.l1d_size, > assoc = options.l1d_assoc, > block_size=options.cacheline_size) > > if options.l3cache: > if options.cpu_type == "arm_detailed": > system.cpu[i].l2 = O3_ARM_v7aL2(size = > options.l2_size, assoc = options.l2_assoc, > > block_size=options.cacheline_size) > else: > system.cpu[i].l2 = L2Cache(size = options.l2_size, > assoc = options.l2_assoc, > > block_size=options.cacheline_size) > > if buildEnv['TARGET_ISA'] == 'x86': > if options.l3cache: > system.cpu[i].addTwoLevelCacheHierarchy(icache, > dcache, system.cpu[i].l2, > > PageTableWalkerCache(), > > PageTableWalkerCache()) > else: > system.cpu[i].addPrivateSplitL1Caches(icache, dcache, > > PageTableWalkerCache(), > > PageTableWalkerCache()) > else: > if options.l3cache: > system.cpu[i].addTwoLevelCacheHierarchy(icache, > dcache, system.cpu[i].l2) > else: > system.cpu[i].addPrivateSplitL1Caches(icache, dcache) > system.cpu[i].createInterruptController() > if options.l3cache: > system.cpu[i].connectAllPorts(system.tol3bus, system.membus) > else: > if options.l2cache: > system.cpu[i].connectAllPorts(system.tol2bus, system.membus) > else: > system.cpu[i].connectAllPorts(system.membus) > > return system > > > *config.ini* > * > * > [root] > type=Root > children=system > full_system=false > time_sync_enable=false > time_sync_period=100000000000 > time_sync_spin_threshold=100000000 > > [system] > type=System > children=cpu l3 membus physmem tol3bus > boot_osflags=a > init_param=0 > kernel= > load_addr_mask=1099511627775 > mem_mode=atomic > memories=system.physmem > num_work_ids=16 > readfile= > symbolfile= > work_begin_ckpt_count=0 > work_begin_cpu_id_exit=-1 > work_begin_exit_count=0 > work_cpus_ckpt_count=0 > work_end_ckpt_count=0 > work_end_exit_count=0 > work_item_id=-1 > system_port=system.membus.slave[0] > > [system.cpu] > type=AtomicSimpleCPU > children=dcache dtb dtb_walker_cache icache interrupts itb > itb_walker_cache l2cache l2cache toL2Bus tracer workload > checker=Null > clock=500 > cpu_id=0 > defer_registration=false > do_checkpoint_insts=true > do_quiesce=true > do_statistics_insts=true > dtb=system.cpu.dtb > fastmem=false > function_trace=false > function_trace_start=0 > interrupts=system.cpu.interrupts > itb=system.cpu.itb > max_insts_all_threads=0 > max_insts_any_thread=0 > max_loads_all_threads=0 > max_loads_any_thread=0 > numThreads=1 > phase=0 > profile=0 > progress_interval=0 > simulate_data_stalls=false > simulate_inst_stalls=false > system=system > tracer=system.cpu.tracer > width=1 > workload=system.cpu.workload > dcache_port=system.cpu.dcache.cpu_side > icache_port=system.cpu.icache.cpu_side > > [system.cpu.dcache] > type=BaseCache > addr_ranges=0:18446744073709551615 > assoc=8 > block_size=64 > clp_nChance=1 > forward_snoops=true > hash_delay=1 > is_top_level=true > latency=1000 > max_miss_count=0 > mshrs=10 > prefetch_on_access=false > prefetcher=Null > prioritizeRequests=false > repl=Null > repl_Policy=LRU > size=32768 > subblock_size=0 > system=system > tgts_per_mshr=20 > trace_addr=0 > two_queue=false > write_buffers=8 > cpu_side=system.cpu.dcache_port > mem_side=system.cpu.toL2Bus.slave[1] > > [system.cpu.dtb] > type=X86TLB > children=walker > size=64 > walker=system.cpu.dtb.walker > > [system.cpu.dtb.walker] > type=X86PagetableWalker > system=system > port=system.cpu.dtb_walker_cache.cpu_side > > [system.cpu.dtb_walker_cache] > type=BaseCache > addr_ranges=0:18446744073709551615 > assoc=2 > block_size=64 > clp_nChance=1 > forward_snoops=true > hash_delay=1 > is_top_level=true > latency=1000 > max_miss_count=0 > mshrs=10 > prefetch_on_access=false > prefetcher=Null > prioritizeRequests=false > repl=Null > repl_Policy=LRU > size=1024 > subblock_size=0 > system=system > tgts_per_mshr=12 > trace_addr=0 > two_queue=false > write_buffers=8 > cpu_side=system.cpu.dtb.walker.port > mem_side=system.cpu.toL2Bus.slave[3] > > [system.cpu.icache] > type=BaseCache > addr_ranges=0:18446744073709551615 > assoc=8 > block_size=64 > clp_nChance=1 > forward_snoops=true > hash_delay=1 > is_top_level=true > latency=1000 > max_miss_count=0 > mshrs=10 > prefetch_on_access=false > prefetcher=Null > prioritizeRequests=false > repl=Null > repl_Policy=LRU > size=32768 > subblock_size=0 > system=system > tgts_per_mshr=20 > trace_addr=0 > two_queue=false > write_buffers=8 > cpu_side=system.cpu.icache_port > mem_side=system.cpu.toL2Bus.slave[0] > > [system.cpu.interrupts] > type=X86LocalApic > int_latency=1000 > pio_addr=2305843009213693952 > pio_latency=1000 > system=system > int_master=system.membus.slave[2] > int_slave=system.membus.master[2] > pio=system.membus.master[1] > > [system.cpu.itb] > type=X86TLB > children=walker > size=64 > walker=system.cpu.itb.walker > > [system.cpu.itb.walker] > type=X86PagetableWalker > system=system > port=system.cpu.itb_walker_cache.cpu_side > > [system.cpu.itb_walker_cache] > type=BaseCache > addr_ranges=0:18446744073709551615 > assoc=2 > block_size=64 > clp_nChance=1 > forward_snoops=true > hash_delay=1 > is_top_level=true > latency=1000 > max_miss_count=0 > mshrs=10 > prefetch_on_access=false > prefetcher=Null > prioritizeRequests=false > repl=Null > repl_Policy=LRU > size=1024 > subblock_size=0 > system=system > tgts_per_mshr=12 > trace_addr=0 > two_queue=false > write_buffers=8 > cpu_side=system.cpu.itb.walker.port > mem_side=system.cpu.toL2Bus.slave[2] > > [system.cpu.l2cache] > type=BaseCache > addr_ranges=0:18446744073709551615 > assoc=8 > block_size=64 > clp_nChance=0 > forward_snoops=true > hash_delay=1 > is_top_level=false > latency=10000 > max_miss_count=0 > mshrs=20 > prefetch_on_access=false > prefetcher=Null > prioritizeRequests=false > repl=Null > repl_Policy=LRU2 > size=262144 > subblock_size=0 > system=system > tgts_per_mshr=12 > trace_addr=0 > two_queue=false > write_buffers=8 > cpu_side=system.cpu.toL2Bus.master[0] > mem_side=system.tol3bus.slave[0] > > [system.cpu.l2cache] > type=BaseCache > addr_ranges=0:18446744073709551615 > assoc=8 > block_size=64 > clp_nChance=0 > forward_snoops=true > hash_delay=1 > is_top_level=false > latency=10000 > max_miss_count=0 > mshrs=20 > prefetch_on_access=false > prefetcher=Null > prioritizeRequests=false > repl=Null > repl_Policy=LRU2 > size=262144 > subblock_size=0 > system=system > tgts_per_mshr=12 > trace_addr=0 > two_queue=false > write_buffers=8 > cpu_side=system.cpu.toL2Bus.master[0] > mem_side=system.tol3bus.slave[0] > > [system.cpu.toL2Bus] > type=CoherentBus > block_size=64 > clock=1000 > header_cycles=1 > use_default_range=false > width=64 > master=system.cpu.l2cache.cpu_side > slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side > system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side > > [system.cpu.tracer] > type=ExeTracer > > [system.cpu.workload] > type=LiveProcess > cmd=tests/test-progs/hello/bin/x86/linux/hello > cwd= > egid=100 > env= > errout=cerr > euid=100 > executable=tests/test-progs/hello/bin/x86/linux/hello > gid=100 > input=cin > max_stack_size=67108864 > output=cout > pid=100 > ppid=99 > simpoint=0 > system=system > uid=100 > > [system.l3] > type=BaseCache > addr_ranges=0:18446744073709551615 > assoc=16 > block_size=64 > clp_nChance=0 > forward_snoops=true > hash_delay=1 > is_top_level=false > latency=30000 > max_miss_count=0 > mshrs=20 > prefetch_on_access=false > prefetcher=Null > prioritizeRequests=false > repl=Null > repl_Policy=PELIFO > size=1048576 > subblock_size=0 > system=system > tgts_per_mshr=12 > trace_addr=0 > two_queue=false > write_buffers=8 > cpu_side=system.tol3bus.master[0] > mem_side=system.membus.slave[1] > > [system.membus] > type=CoherentBus > block_size=64 > clock=1000 > header_cycles=1 > use_default_range=false > width=64 > master=system.physmem.port[0] system.cpu.interrupts.pio > system.cpu.interrupts.int_slave > slave=system.system_port system.l3.mem_side > system.cpu.interrupts.int_master > > [system.physmem] > type=SimpleMemory > conf_table_reported=false > file= > in_addr_map=true > latency=30000 > latency_var=0 > latency_wr=600000 > null=false > range=0:536870911 > zero=false > port=system.membus.master[0] > > [system.tol3bus] > type=CoherentBus > block_size=64 > clock=1000 > header_cycles=1 > use_default_range=false > width=64 > master=system.l3.cpu_side > slave=system.cpu.l2cache.mem_side > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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