Hi all,
Patch http://reviews.gem5.org/r/1376/ (changeset 9153) adds a test to
identify load as control instructions if it write to the PC register.
But VLDR (vector load, floating point instruction) (and possibly others
instructions) are constructed using the same code. If this instruction
write to the FP reg 15, then its _dest variable is 15 (= INTREG_PC),
then the instruction is marked as being a control instruction, which is
wrong (I believe there is no floating point branch instruction).
However, I don't really know how to correct that as this part of the
instruction generator is quite obscure for me.
For the moment, I will just add a test that check if the control flag
and the floating point flag are set and disable the control flag in that
case. But it is not a good solution :)
Does anyone have an idea on how to correct that?
Nathanaël
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