Hi Madarbux,
If you are using the classic memory model, then you can get the memory
address from the packet by using getAddr(). You can refer to packet.hh
and abstract_mem.hh for the detail.
-Tao
On 02/05/2013 05:54 AM, ridwan madarbux wrote:
Dear Sir,
My name is Ridwan and I am a PhD student at University
College London. I am quite new at using Gem5 and I am finding it quite
difficult for the time being to modify what I want. I am currently
investigating the sequence of data and control messages that each core
sends to one another when there is normal running of PARSEC benchmark
on a linux kernel and in order to generate a trace file, I am adding
debug flags to the gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
document. Now the problem is that I know nearly all the variables that
I want to be in the tracefile but I am missing the memory address. Do
you know what variable could give me the memory address? I understand
that messages will be sent in sequence between the cores, for example
let us say, core X sends a control request to core Y, core Y will send
a control response to core X and core X will send the data response to
core Y followed sometimes with a control unblock message. Now, I want
to be able to identify these sequences and as I understand, the way to
do so would be to note the memory address since all the different
sequences will have different memory addresses but all the messages in
one sequence will have the same memory address. Can you please help me?
Thank you in advance for your help.
Yours sincerely,
Madarbux Muhammad Ridwan.
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