Alright... Seems like I was thinking too much about compiled programming languages. I think the reason gem5 config files are written in python is because of its interpreted nature. We can define/use class members on the fly. Unlike, in c++ we need to define them.
The only thing we need to consider here is that one side of the cache hierarchy should be connected to cpu and the other memory. We can define whatever variable we want in the middle (to our confort) as long as we connect them with using busses,ports etc. 2013/1/6 mehmet basaran <[email protected]> > Hi all, > > It is probably equally painful for me to write this and you to answer. > So... I need your patience. > > I am trying to implement 8 core system with 3 level cache hierarchy. I > don't use Ruby. > L3 will be shared > L2i and L2d will be shared among only 2 cores > L1i and L1d will be private. > > In default cache hierarchy, we have 1 bus (between l1 and l2) which is > connected to system directly. Now I need to have 4 lvl2 busses. In > addition, l2 data and ins caches are separate. > > Normally I can refer to l2 cache by -> system.l2 > Now I have to get/set specific cache. How can I do it ? I tried; > > >> system.l2icache[i] > >> system.cpu[i].l2dcache > > but no luck. Any pointers on how to do this would be great. > > Thanks > Mehmet >
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