Hi Amin,
I know and it's obvious that the files should be different! My question
was that I want to find the exact reasons that cause these differences.
But, thank you for the names. I will look at those files first.
Another thing I should mention and which is strange is that the
benchmark with higher frequency is running slower! And, the lines I
mentioned previously are those extra tasks that are simulated with the
higher frequency, and I don't know why!
Cheers
Negar
On 2/13/2013 7:41 PM, Amin Farmahini wrote:
When you change the frequency, you may get a different trace file.
This is pretty normal.
For your case, you may take a look at src/mem/bus.cc and
src/sim/eventq_impl.hh as a starting point.
Thanks,
Amin
On Wed, Feb 13, 2013 at 9:38 AM, Negar Miralaei <[email protected]
<mailto:[email protected]>> wrote:
Hi All,
I'm wondering if anybody could give me some points to start
digging into some parts of gem5 code! I've got two different trace
outputs from running one benchmark (from CPU2000) with two
different frequencies on the Timing CPU with ARM platform. The
differences between these two trace files are as follows.
49998: system.mainCpu.icache_port: Received timing response 0x91664
/49998: Event_30: Timing CPU icache tick event scheduled @ 50904//
//49998: system.membus.respLayer.wrapped_event: EventWrapped event
scheduled @ 52000//
//49998: system.membus.respLayer: The bus is now busy from tick
49998 to 52000/
50904: system.mainCpu: Complete ICache Fetch for addr 0x91664
Those 3 middle lines are just appear in one of those trace files
which means it's trying to do an extra scheduling for one of the
frequencies. I'm trying to find the reason for this extra
scheduling by looking at the source codes in gem5 (maybe eventq
and timingcpu) but, there are many classes and functions which is
confusing for me as a fresher in gem5! I'd be so thankful if you
could have any opinions or you think I should focus on debugging
some specific functions or objects.
Thanks
Negar
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