Hi, I'm hacking classic cache model to implement my own cache design. I'm using a two level cache hierarchy and simple memory. I met a very strange assertion fail which I could not figure it out. The failed assertion is as follows:
void MSHR::clearDownstreamPending(): Assertion `downstreamPending' failed If I trace back the calling stack, it is called by sendDeferredPacket() function in cache_impl.hh. I have figured out some more detailed information. This function basically sends out request from either miss queue or write buffer. In this specific case, it gets a timing packet from L2 cache write buffer, therefore it is a L2 writeback packet, and MSHR->isForwardNoResponse() is true (do not need response). Also, no new bus packet is generated and the original packet is forwarded to next level (in my case, it is a simple memory). It turns out after calling the function masterPort.sendTimingReq(pkt), pkt is modified and MSHR->isForwardNoResponse() (which depends on mshr->getTarget()->pkt) is no longer true (pkt->cmd becomes ReadReq). I was wondering is there any way that the function sendTimingReq(pkt) can modify the attribute of the packet (such as change pkt->cmd)? By the way, Before successfully send the request, sendDeferredPacket retries several times. Thanks in advance! Best regards Fangfei
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