I'm currently using the ARM cpu and the detailed configuration, example input as:
./build/ARM/gem5.fast ... configs/example/fs.py ... --caches --cpu-type=detailed --l1d_size=32kB --l1i_size=32kB --l2cache --l2_size=2048kB --clock=0.75GHz I'm trying to understand the exact configuration here - Does each l1 cache have a separate port going to the cpu, and a separate port going to the l2 cache? If there were no l2 cache, would each l1 cache have a direct port to memory? In other words, I'm trying to determine which, if any, of these figures accurately portrays this memory configuration. http://imgur.com/a/8WVeR
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