which version of gem5 are you using? both files should be located in
src/mem.
For your question, the answer is "Yes". Even though the existing DRAM
model (simple_dram.cc) doesn't distinguish memory controller and DIMMs,
you can start from it to see how memory requests are handled and how
memory latency are modeled.
Alternatively, our memory simulator NVMain does decouple memory
controller from DIMMs so that it allows you to develop a custom memory
controller very quickly. You can get more information on
http://www.nvmain.org.
-Tao
On 02/25/2013 01:23 PM, Shivam Agarwal wrote:
Thanks Tao
I do not find SimpleDRAM.py and Simple_dram.cc . Also I wish to add
DRAM controller (and customize it ) in between last level cache and
DRAM as my project is about developing DDR3 Controller strategies. Can
this be done without using ruby?
Thanks
Shivam
On Mon, Feb 25, 2013 at 11:29 PM, Tao Zhang <[email protected]
<mailto:[email protected]>> wrote:
Hi Shivam,
gem5 has two different memory systems: classic memory and ruby
memory. You cannot use both simultaneously.
http://www.gem5.org/General_Memory_System
Generally, you can directly use the existing DRAM model in classic
memory (SimpleMemory, SimpleDDR3, SimpleLPDDR2_S4, see
src/mem/SimpleDRAM.py and SimpleMemory.py) OR you can attach your
own DRAM model into classic memory like src/mem/simple_dram.cc does.
-Tao
On 02/25/2013 12:48 PM, Shivam Agarwal wrote:
Hello everyone
I want to simulate memory system consisting of L1, L2 (and
possibly L3) and DRAM. I was able to add L3 cache in
CacheConfig.py, however it seems I can't add DRAM using classic
memory model. I have read about ruby on wiki. Kindly tell me how
can I get started with ruby.
Best Regards
Shivam Agarwal
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